Structure of MIS capacitor with capacitance being variable and manufacturing method thereof

Abstract

The invention discloses a manufacturing method of an MIS capacitor with the capacitance being variable, which comprises the steps of 1) growing an N-type lightly doped epitaxy on an N-type heavily doped substrate; 2) growing a sacrificial oxidation layer; 3) defining an N-type ion implantation region and vertically implanting N-type ions; 4) implanting the N-type ions by an oblique angle; 5) removing a photoresist and carrying out thermal annealing; 6) removing the sacrificial oxidation layer and further depositing an oxidation layer; and 7) depositing a metal layer. The invention further discloses a structure of the MIS capacitor. A transverse wave-shaped concentration gradient of the implanted ions is formed in an N-type lightly doped epitaxial layer of the MIS capacitor through the vertical N-type ion implantation and the angled N-type ion implantation and diffusion after implantation. The structure enables the capacitance of the MIS capacitor to be increased along with increase in impressed voltage, the capacitance forms complementation with output capacitance of an RFLDMOS, and the nonlinearity of the output capacitance along with voltage can be reduced through parallel connection and internal matching of the MIS capacitor and the output capacitance of the RFLDMOS.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a structure and a manufacturing method of an MIS capacitor with variable capacitance applied to RFLDMOS technology. Background technique [0002] In RFLDMOS process, Coss-V d curve like figure 1 As shown, it can be seen from the figure that the output capacitance will increase with the drain voltage V d If a capacitor with a voltage coefficient close to zero is connected in parallel at the output end at this time for internal matching, it will not be able to match the best value within the working voltage range of RFLDMOS, causing the power amplifier output power, gain and reduction in efficiency, etc. [0003] MIS capacitors usually used for internal matching use silicon oxide or silicon nitride as the dielectric layer, and the substrate is a uniformly doped silicon substrate. The capacitance value will not change with the change of voltage, so th...

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Problems solved by technology

[0002] In RFLDMOS process, Coss-V d curve like figure 1 As shown, it can be seen from the figure that the output capacitance will increase with the drain voltage V d If a capacitor with a voltage coefficient close to zero is connected in parallel at the output end at this time for internal matching, it will not be able to match the best value within the working voltage range of RFLDMOS, causing the power amplifier output power, gain and reduction in efficiency, etc.

[0003] The MIS capacitor usually used for internal matching uses silicon oxide or silicon nitride as the dielectric layer, and the substrate is a uniformly doped silicon substrate. The capacitance value will not change with the voltage change, so that the operating voltage of the power amplifier cannot range for the best fit

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