83results about How to "Improve chip performance" patented technology

A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, in contrast with the conventional fully etched stencil-like lead frames, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal. The use of the instant partially patterned lead frame in making ELP, ELPF and ELGA-type CSPs is also disclosed.

A quad flat no-lead chip carrier for a wire-bonded chip package is provided. The chip carrier comprises a conductive plate, a plurality of conductive columns and a plurality of dielectric walls. A chip is attached to the conductive plate. The conductive plate furthermore has a plurality of columnar through holes distributed around a chip-bonding region. The conductive columns are set up within the columnar through holes. The dielectric walls are set up between the sidewall of the conductive columns and the inner surface of the columnar through holes. The chip is electrically connected to the conductive columns via conductive wires. The bottom end of the conductive columns serves as input/output contacts for connecting with external contacts. The chip carrier is able to increase overall density of the input/output contacts and improve the electrical performance of the chip package.

Embodiments of the present invention are directed to a process for forming small diameter vias at low temperatures. In preferred embodiments, through-substrate vias are fabricated by forming a through-substrate via; and depositing conductive material into the via by means of a flowing solution plating technique, wherein the conductive material releases a gas that pushes the conductive material through the via to facilitate plating the via with the conductive material. In preferred embodiments, the fabrication of the substrate is conducted at low temperatures.

A solution for determining minimum operating voltages due to performance/power requirements would be valid for a wide range of actual uses. The solution includes a test flow methodology for dynamically reducing power consumption under applied conditions while maintaining application performance via a BIST circuit. There is additionally provided a test flow method for dynamically reducing power consumption to the lowest possible stand-by/very low power level under applied conditions that will still be sufficient to maintain data/state information. One possible application would be for controlling the voltage supply to a group of particular circuits on an ASIC (Application Specific Integrated Circuit). These circuits are grouped together in a voltage island where they would receive a voltage supply that can be different from the voltage supply other circuits on the same chip are receiving. The same solution could be applied to a portion of a microprocessor (the cache logic control, for example).

An Infiniband switch can be provided. The switch can have an input port logic unit for determining an output virtual lane for a received packet and for storing a descriptor of the determined output virtual lane in a packet field not protected by a checksum field of the packet. The switch can also have a routing unit for transferring the received packet to an output port corresponding to the determined output virtual lane. Additionally, the switch can have an output port logic unit for simultaneously checking the integrity of the packet transferred through the routing unit and calculating a new value for the checksum with the descriptor moved to a correct packet field, which field is included in the calculation of the checksum.

The present invention aims to provide a tire rubber composition that achieves a good balance of grip performance (especially, wet grip performance), abrasion resistance, cut and chip resistance, low rolling resistance, and kneadability, and a pneumatic tire using the same. The composition comprise: a rubber component including a styrene-butadiene rubber modified by a compound of formula (1): and a non-modified styrene-butadiene rubber; a filler including silica, the filler being in an amount of 80 parts by mass or less per 100 parts by mass of the rubber component; and sulfur in an amount of 0.5-1.5 parts by mass per 100 parts by mass of the rubber component, the modified styrene-butadiene rubber having a bound styrene content of 20-40% by mass and a vinyl content of 30-65% by mass, and the non-modified styrene-butadiene rubber having a bound styrene content of 25-45% by mass and a vinyl content of 10-50% by mass.

The invention discloses a method for powder metallurgy preparation of a self-lubricating bearing material, belonging to the field of lubricating materials. According to the method, a traditional powder metallurgy method is adopted, and the method comprises the following steps of: mixing and annealing iron powder with an appropriate amount of iron sulfide, ferromanganese powder and alloy powder; mixing the annealed powder with an appropriate amount of graphite; pressing and sintering to obtain the self-lubricating bearing material. The raw materials are inexpensive, the process is simple, the parameters are easy to control, and the production process is safe and environment-friendly, so that the method is suitable for large-scale industrial production. In the annealing process, the mixed powder reacts to generate FeS and MnS, and good lubricating and antifriction effects are achieved; meanwhile, the existence of MnS can significantly improve the cutting performance of the bearing material and reduce the abrasion of a cutter. The self-lubricating bearing material prepared by the method disclosed by the invention can be widely applied to mechanical equipment for iron and steel, metallurgy, energy sources and the like, and is particularly suitable for occasions requiring oil-free lubrication.

The invention provides a novel self-chip-removal machine tool. The cutting efficiency is effectively improved through vibrating drilling, and the novel self-chip-removal machine tool is smooth in chip removal and high in chip removal speed. A guide rod is arranged on the machine frame. An upper supporting plate is connected to the periphery of the guide rod in a vertical sliding and sleeving mode. The two ends of each spring are fixedly connected to the upper supporting plate and a machine frame respectively. A first drive device is arranged on the machine frame. A cam mechanism comprises a cam and a driven rod. The cam is connected to the periphery of an output shaft of the first drive device in a sleeving mode and is driven by the first drive device to rotate. One end of the driven rod is arranged on the upper supporting plate, and the other end of the driven rod abuts against the cam. A second drive device is arranged on the upper supporting plate and can drive a lower supporting plate to move in the axial direction of the guide rod. A third drive device is arranged on the lower supporting plate and can drive a drilling assembly to rotate. A drill stem is connected with an output shaft of the third drive device. A drill bit is arranged on the side, away from the third drive device, of the drill stem. The novel self-chip-removal machine tool is used for arranging a clamping piece on the machine frame, wherein the clamping piece is used for clamping workpieces.

An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer overlying the plurality of IMD layers and the plurality of copper metal layers; a first power/ground ring of a circuit block of the integrated circuit chip formed in a topmost layer of the plurality of copper metal layers; a second power/ground ring of the circuit block of the integrated circuit chip formed in an aluminum layer over the first passivation layer; and a second passivation layer covering the second power/ground ring and the first passivation layer.

The invention discloses a cage pocket structure with stress buffer grooves and a pocket machining technology of the structure. The problems that an existing cylindrical roller bearing cage pocket structure is large in abrasion to a machining tool and complex in machining technology process are solved. The cage pocket structure with the stress buffer grooves is characterized in that the pocket is a straight pocket, and the stress buffer grooves with the radius of R2 are machined on the four corners of the pocket; according to the pocket machining technology of the cage pocket structure with the stress buffer grooves, a drill bit is selected, and according to the stress buffer groove positions required by the drawing, on a numerical control machining center, the drill bit is used for carrying out stress buffer groove machining on the pocket of a cylindrical roller bearing cage; the cage is drilled on the numerical control machining center, and the drilling size should ensure that the single-side milling allowance ranges from 0.1 mm to 0.25 mm; a milling cutter is used for feeding from the center of the pocket, and pocket machining is completed through milling; and the machined pocket is detected. The cage pocket structure is used for machining of the cage pocket.

Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.