AI calculation graph sorting method and device, equipment and storage medium

Abstract

The embodiment of the invention discloses an AI calculation graph sorting method and device, equipment and a storage medium. The method comprises the steps: obtaining a calculation graph based on dataflow architecture, and enabling the calculation graph to comprise a plurality of calculation nodes; performing topological sorting on the calculation graph to obtain a first arrangement sequence of the calculation graph; determining a second arrangement sequence of a plurality of branch computing nodes according to the branch sequence of the plurality of branches in the calculation graph; and replacing the arrangement sequence of the branch computing nodes in the first arrangement sequence with a second arrangement sequence corresponding to the branch computing nodes to obtain a target arrangement sequence of the calculation graph. According to the embodiment of the invention, topological sorting and branch sorting are carried out on the calculation graph, so that sorting of the calculation graph based on the data flow architecture is realized, the execution sequence of each calculation node in the calculation graph can be uniquely determined, and the chip performance based on the data flow architecture is improved.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of artificial intelligence, and in particular to a sorting method, device, device and storage medium for AI calculation graphs. Background technique [0002] The deep learning model is essentially a computational graph, such as the convolutional neural network model, which is essentially a directed acyclic computational graph. The computational graph contains a large number of computational nodes, each of which represents a computational operation, and has input dependencies. , that is, the input nodes of the current computing node are all calculated before the current computing node can be executed. [0003] At present, the development of artificial intelligence chips is mostly based on the instruction set architecture of the current CPU (Central Processing Unit, central processing unit) and GPU (Graphics Processing Unit, graphics processing unit), and the CPU and GPU usually have ...

AI Technical Summary

Problems solved by technology

[0004] In recent years, an artificial intelligence chip developed based on the data flow architecture has attracted much attention because of its high utilization rate and low delay. However, the data flow architecture and the instruction set architecture are not the same architecture. The instruction control unit and cache mechanism of the instruction set architecture It cannot be reused in the data flow architecture, and the artificial intelligence chip developed based on the data flow architecture does not have an instruction control unit, and only accepts the order of the pre-optimized calculation graph for execution. Therefore, there is an urgent need for a processing method to advance the calculation graph Optimize the ordering of nodes so that the artificial intelligence chip developed based on the data flow architecture can normally operate on the calculation graph

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