33results about How to "Effective mass reduction" patented technology

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

The invention relates to a compressive strain Si PMOS device based on channel crystal direction selection and a preparation method thereof. The preparation method comprises: selecting a single crystal Si substrate whose crystal plane is (001); growing a relaxed SiC epitaxial layer on the surface of the single crystal Si substrate; growing a strained Si layer on the surface of the relaxed SiC epitaxial layer; and growing a strained Si layer on the surface of the strained Si layer. Continuously grow the gate dielectric layer and the gate layer, and use the etching process to etch the gate layer and the gate dielectric layer to form the gate; use the self-alignment process to perform P-type ion implantation on the device surface different from the gate region to form the source and the drain; after passivation treatment on the surface of the device, a compressively strained SiPMOS device based on channel crystal orientation selection is formed. The present invention solves the traditional relaxation Si 1‑x Ge x The problem of poor hole mobility enhancement effect of substrate-induced biaxial strain Si material. At the same time, the [110] crystal orientation with low conductivity and effective mass is used as the biaxial Si / (001)Si 1‑x C x PMOS channel crystal orientation significantly improves biaxial strain Si / (001)Si 1‑x C x Material mobility and device performance.

The invention discloses an organic intercalation method, device, material, testing method, application and solar panel, and relates to the field of materials, mainly in that the stability and photoelectric performance of the material can be improved, and the band gap of the material can be determined through the performance test conclusion. The width is adjusted to obtain a material that meets the band gap width requirements. The method includes: obtaining the three-dimensional geometric structure of the material; inserting organic molecules in the three-dimensional geometric structure according to the set number of inorganic layers, and reducing the three-dimensional geometric structure to a quasi-two-dimensional geometric structure; the organic molecules are used for Reduce the electronically effective mass of the material and / or increase the stability of the material. The present invention is applicable to the organic intercalation of materials.

Dynamic tag compare circuits employing P-type Field-Effect Transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and thus increased circuit performance, are provided. A dynamic tag compare circuit may be used or provided as part of searchable memory, such as a register file or content-addressable memory (CAM), as non-limiting examples. The dynamic tag compare circuit includes one or more PFET-dominant evaluation circuits comprised of one or more PFETs used as logic to perform a compare logic function. The PFET-dominant evaluation circuits are configured to receive and compare input search data to a tag(s) (e.g., addresses or data) contained in a searchable memory to determine if the input search data is contained in the memory. The PFET-dominant evaluation circuits are configured to control the voltage / value on a dynamic node in the dynamic tag compare circuit based on the evaluation of whether the received input search data is contained in the searchable memory.

The invention relates to a compressive-strain Si CMOS device based on channel crystal orientation selection and a preparation method thereof. The preparation method comprises: selecting a Si substrate; growing a relaxed Si epitaxial layer; growing a strained Si layer; forming a shallow trench isolation; forming an N type well region and a P type well region by using an ion implantation process; growing a gate dielectric layer and a gate electrode continuously on the surface of the strained Si layer and etching the gate layer and the gate dielectric layer by using an etching process to form gates respectively; forming a PMOS source-drain region and an NMOS source-drain region based on a self-aligned process; and forming source-drain contact in the source-drain regions and then forming a CMOS device finally. Therefore, a problem of poor hole mobility enhancement effect of the biaxial strained Si material due to the traditional relaxed Si(1-x)Gex substrate is solved. The low-conductivity effective-quality [110] crystal orientation is used as biaxial strained Si / (001) Si(1- x)Cx PMOS channel orientation and the high-electron-mobility [100] crystal orientation as biaxial strained Si / (001) Si(1-x)CxNMOS channel orientation, so that the mobility ratio of the biaxial strained Si / (001) Si(1-x)Cx material and the performance of the device are improved.

The invention provides a double-gate p-channel MOSFET with a compression strain thin film strain source and a preparation method of the double-gate p-channel MOSFET with the compression strain thin film strain source. The MOSFET comprises a source region, a drain region, a conducting channel region, a gate dielectric layer, a grid electrode, an insulating dielectric layer and a compression strain thin film strain layer. The gate dielectric layer is formed on a first surface of a semiconductor material and located on the side face of a first conducting surface and the side face of a second conducting surface of the conducting channel region. The grid electrode is formed on the first surface of the semiconductor material and located on the side face of the gate dielectric layer. The insulating dielectric layer is formed on the side wall of the grid electrode, the side wall of a source electrode and the side wall of a drain electrode. The compression strain thin film strain layer is formed on the side wall of the insulating dielectric layer and used for leading compression strain in the channel direction into the conducting channel region. The surface of the MOSFET is covered with the compression strain thin film strain layer, and the large compression strain in the channel direction is led into the conducting channel region; as a result, effective mass of holes can be reduced, the migration rate of the holes is increased, the working current of the MOSFET is increased, and on-resistance is lowered.

The invention discloses a method for improving an erasing speed of an SONOS (Silicon Oxide Nitride Oxide Silicon) by utilizing a strained silicon technology. The method is characterized by comprising the following steps of: after manufacturing a sidewall of a grid electrode on a P-type substrate forming a plurality of shallow channel isolation regions, (1) depositing a baffle layer to cover a transistor; (2) etching to remove the baffle layer covering above an NMOS (N-channel Metal Oxide Semiconductor) region to expose the NMOS region; (3) etching silicon of active regions on two sides of the grid electrode of the NMOS region; (4) depositing silicon carbide at the active regions through a selectivity epitaxy process; and (5) carrying out high-temperature annealing to enable the silicon carbide to generate tensile stress on a channel. According to the method for increasing the erasing speed of the SONOS by utilizing the strained silicon technology, disclosed by the invention, an energy band of silicon is broken up so that effective mass of electron in the direction of the channel is reduced; simultaneously, energy valley scattering probability of the electron is also reduced, and mobility of the electron of the SONOS unit transistor is remarkably improved, thus the SONOS programming efficiency and speed of a hot electron injection mechanism are improved.

The invention provides a lateral double-diffused field effect transistor, a manufacturing method, a chip and a circuit. The transistor includes: a substrate with a high-voltage N-type well; a first N-type drift region, a P-type body region and a second The N-type drift region is formed in the high-voltage N-type well; the first strained region is formed in the first N-type drift region; the second strained region is formed in the second N-type drift region; the first drain is formed in the second N-type drift region. One strain region; the second drain, formed in the second strain region; the first source and the second source, formed in the P-type body region; the substrate electrode, formed in the first source and the second source between; the first gate, formed on the upper surface of the first N-type drift region and the P-type body region; the second gate, formed on the upper surface of the P-type body region and the second N-type drift region, and the second gate A space is formed between the electrode and the first grid. The transistor provided by the invention can improve the mobility of carriers in the channel, and improve the driving ability and speed of the transistor.

The invention relates to the technical field of semiconductor devices, in particular to an III-nitrides p-type ohmic electrode structure with low contact resistance. The direction of an electrode pattern line body of the electrode structure is consistent with a first crystal orientation or a second crystal orientation and an equivalent crystal orientation of the first crystal orientation and the second crystal orientation of III-nitrides; after clockwise rotating for 120 degrees, the first crystal orientation is parallel to the second crystal orientation; and a bonding wire electrode part of the electrode structure is located at the geometric center of the electrode structure or at a cross point of any electrode pattern line body. The electrode structure in the invention aims to obtain good ohmic contact characteristic on the p-type III-nitrides material; the high tunneling probability characteristic of a hole in the crystal orientation and the equivalent crystal orientation of the III-nitrides material is effectively utilized by the proposed electrode structure along the crystal orientation, thereby reducing electrical resistivity of ohmic contact.