Wordline negative boost write-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) write port(s), and related systems and methods

Abstract

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

Description

PRIORITY APPLICATION[0001]The present application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application Ser. No. 62 / 119,763 filed on Feb. 23, 2015 and entitled “WRITE-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) WRITE PORT(S), AND RELATED SYSTEMS AND METHODS,” which is incorporated herein by reference in its entirety.BACKGROUND[0002]I. Field of the Disclosure[0003]The technology of the disclosure relates generally to memory systems employing addressable static memory bit cells for reading and writing data, and more particularly to write-assist circuits for mitigating write contention conditions when writing to bit cells.[0004]II. Background[0005]Supply voltage (i.e., Vdd) scaling is an effective technique for maximizing processor energy efficiency across all market segments, ranging from small, embedded cores in a system-on-a-chip (SoC) to large multicore servers. As supply voltage in processor-based systems is reduc...

AI Technical Summary

Benefits of technology

This patent involves an improvement to memory cells in a processor-based system. By using a specific type of transistor called PFET, the technology can be scaled down to improve memory performance. The PFET transistor has higher drive current than NFET, which means it can handle more data. To handle these larger amounts of data, the patent also describes a circuit that helps reduce the strain on the transistor during a write operation, which can improve memory performance. The method involves charging the access node of the transistor with data and activating the gate to transfer the data to the storage circuit. The patent also introduces a negative boost to assist in transferring data from the access node to the storage circuit. This can ultimately lead to faster memory writing times and better performance. Additionally, the patent describes a method to reduce write contention in the memory cells, which can help decrease power consumption and improve energy efficiency in the processor system. Overall, the patent highlights the technical improvements and performance benefits of using PFET technology and write-assist circuits in memory cells.

Problems solved by technology

This is due to the introduction of strained silicon in FET fabrication to reduce the effective mass of charge carriers.

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