Wordline negative boost write-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) write port(s), and related systems and methods

Abstract

Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).

Description

PRIORITY APPLICATION[0001]The present application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application Ser. No. 62 / 119,763 filed on Feb. 23, 2015 and entitled “WRITE-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) WRITE PORT(S), AND RELATED SYSTEMS AND METHODS,” which is incorporated herein by reference in its entirety.BACKGROUND[0002]I. Field of the Disclosure[0003]The technology of the disclosure relates generally to memory systems employing addressable static memory bit cells for reading and writing data, and more particularly to write-assist circuits for mitigating write contention conditions when writing to bit cells.[0004]II. Background[0005]Supply voltage (i.e., Vdd) scaling is an effective technique for maximizing processor energy efficiency across all market segments, ranging from small, embedded cores in a system-on-a-chip (SoC) to large multicore servers. As supply voltage in processor-based systems is reduc...

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Benefits of technology

[0009]Aspects of the disclosure involve write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s). Related methods and systems are also disclosed. The bit cells are provided in a data array of a memory system in a processor-based system to store data. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. This is due to the introduction of strained silicon in FET fabrication to reduce the effective mass of charge carriers. A write port is a performance critical element in a bit cell. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, write-assist circuits are provided for bit cells having a PFET write port(s). By mitigating or avoiding write contention issues in the bit cells, the voltage supply providing the minimum voltage to the bit cells for operation and data retention can be reduced to reduce power consumption and increase processor energy efficiency.

[0012]In another aspect, a method of writing data to a memory bit cell is provided. The method comprises charging at least one bitline coupled to an access node of one or more PFET access transistors in a memory bit cell with data in response to a write operation. The method also comprises activating a wordline coupled to a gate of the one or more PFET access transistors in response to the write operation to transfer the data from an access node to a storage circuit. The method also comprises negatively boosting a voltage on the wordline in response to the write operation to assist transferring the data from the access node to the storage circuit in response to the write operation.

Problems solved by technology

This is due to the introduction of strained silicon in FET fabrication to reduce the effective mass of charge carriers.

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