Double-gate p-channel MOSFET with compression strain thin film strain source and preparation method thereof

Abstract

The invention provides a double-gate p-channel MOSFET with a compression strain thin film strain source and a preparation method of the double-gate p-channel MOSFET with the compression strain thin film strain source. The MOSFET comprises a source region, a drain region, a conducting channel region, a gate dielectric layer, a grid electrode, an insulating dielectric layer and a compression strain thin film strain layer. The gate dielectric layer is formed on a first surface of a semiconductor material and located on the side face of a first conducting surface and the side face of a second conducting surface of the conducting channel region. The grid electrode is formed on the first surface of the semiconductor material and located on the side face of the gate dielectric layer. The insulating dielectric layer is formed on the side wall of the grid electrode, the side wall of a source electrode and the side wall of a drain electrode. The compression strain thin film strain layer is formed on the side wall of the insulating dielectric layer and used for leading compression strain in the channel direction into the conducting channel region. The surface of the MOSFET is covered with the compression strain thin film strain layer, and the large compression strain in the channel direction is led into the conducting channel region; as a result, effective mass of holes can be reduced, the migration rate of the holes is increased, the working current of the MOSFET is increased, and on-resistance is lowered.

Description

Technical field [0001] The invention relates to the technical field of semiconductor design and manufacturing, in particular to a dual-gate p-channel MOSFET (metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor) with a compressive strain thin film strain source and a preparation method. Background technique [0002] With the rapid and in-depth development of integrated circuit technology, the increase in wafer size and the reduction of chip feature size can meet the requirements of miniaturization, high density, high speed, high reliability and system integration. According to the forecast of the International Technology Roadmap for Semiconductors (ITRS) 2012, when the integrated circuit technology node is below 10 nanometers, strained Si materials can no longer meet the needs, and it is necessary to introduce high carrier mobility material MOSFET to improve Chip performance, such as Ge and GeSn. [0003] GeSn has a higher hole mobil...

AI Technical Summary

Problems solved by technology

However, if the Sn component is too high, the thermal stability of the GeSn material will deteriorate, and the segregation of Sn atoms will easily occur.

Images