92 results about "Common logic" patented technology

A high threshold five transistor SRAM bit cell with cross-coupled inverters has a single BIT line, a common logic 1 supply voltage, and two logic 0 virtual ground source voltages. The BIT line is coupled to the bit cell by a pass transistor. When BIT line and virtual ground lines are not otherwise being used, they are connected to a common standby voltage that substantially lowers bit cell standby leakage. Writing is performed by driving a data signal through the pass transistor and is facilitated by creating a voltage differential on the virtual ground lines. Reading is also performed through the pass transistor wherein the BIT line is initially at the standby voltage, and is then driven lower or higher depending upon the data value stored in the bit cell.

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

The concept of applying fencing logic to Built-In Self Test (BIST) hardware structures for the purpose of segregating defective circuitry and utilizing the remaining good circuitry is a well known practice in the chip design industry. Described herein is a method for verifying that any particular implementation of partial fencing logic actually provides the desired behavior of blocking down-stream impact of all signals from fenced interfaces, and also ensuring that the partial fencing does not inadvertently preclude any common logic from being fully tested.

The invention relates to method and a system for testing a communication protocol interface. The system comprises a testing script module and a universal logic service simulator, wherein the testing script module calls a function of a protocol testing library, simulates the behavior of a client side, and sends a first message to a tested object; the universal logic service simulator receives a second message generated after the first message is processed through the tested object, and transmits the second message to the testing script module; the testing script module simulates the behavior of a service side, and returning a response message of the second message; the universal logic service simulator transmits the response message of the second message to the tested object; and after receiving the response message (processed by the tested object) of the second message, the testing script module checks a response message of the first message. According to the method and the system for testing the communication protocol interface, the universal logic service simulator is adopted to forward messages of various different protocols, different simulators are not required to be developed, and the testing cost can be lowered.

The invention discloses an implementation method of an operation interface of an automatic plant start-up &and shut-down system in a thermal power plant. Due to the common logic, control breakpoint and step sequence logic of the automatic plant start-up &and shut-down system provided by the method as well as the operation interface of the automatic plant start-up &and shut-down system and a modulating control system, the man-machine interactive design of the automatic plant start-up &and shut-down system is simplified, and the applicability of the automatic plant start-up &and shut-down system is improved. In addition, optimal control of a control outputting setting value of the modulating control system can be realized by adopting multiple goal constraint.

An apparatus and method for performing a Hedge Technique Analysis are used to enhance the performance of the functional logic design of a large scale integrated circuit while simplifying the underlying logic. The methodology first runs performance tests on the logic circuitry to assess the timing and characterize the logic paths; next, functional paths are identified and listed; common logic path leaves, twigs, and branches are then identified and ranked by the number of critical paths associated with each; all high ranking common logic path leaves, twigs, and branches are then collapsed; and, timing paths are re-run to characterize the final performance rating of the functional design.

A system and method for coordinating control setting with respect to an automated input/output (I/O) processor. A state machine having a transition algorithm can be configured in association with a storage controller in order to permit multiple entities to safely transmit an I/O request to an I/O device. Specific combinations of control bits associated with a fast path engine can be determined by identifying different modes with respect to the behavior of the fast path engine. Each mode can be assigned as a state with respect to the state machine. An I/O path exception and error condition that can cause transitions between the states can be determined and the transitions can be assigned from one state to another state. A generic logic template can then be configured to govern the transitions with respect to the state machine. The logic can be executed when an event occurs in order to trigger multiple state transition and/or modifications with respect to the hardware control bits of the fast path engine.

Logic circuits based, at least in part, on use of spin-torque transfer (STT) to switch the magnetization—and hence the logic state—of a magnetic material are disclosed. Aspects of the invention include novel STT-based switching devices, new configurations of known STT-based devices into useful logic circuits, common logic circuits and system building blocks based on these new devices and configurations, as well as methods for inexpensively mass-producing such devices and circuits.

The present invention is to provide a logic circuit which assures short-circuit current reduction by using a gate which uniquely fixes the level of each node and also reduces leakage current so that the power is turned on and off quickly. Logic gates of the subject logic circuit are divided into first-type logic gate and second-type logic gates. The first-type logic gate outputs high potential under the specific status and the second-type logic gate outputs low potential under the specific status. Under the state that the high potential is supplied to the first-type logic gates and the low potential is supplied to the second-type logic gates, the power switch MOS is turned on. Further, in case of the adder, the specific status is equal to selecting a constant as an input of the adder. For general logic circuit, specific flip-flops are introduced to implement this specific status.

The invention provides an online service system, which comprises at least two user databases, an interface unit, a database dynamic execution unit, and a common logic unit, wherein each user database comprises a system table, a system field table and a service function table; the interface unit is used for receiving input information of a user; the database dynamic execution unit is used for analyzing the table structure of the user database, dynamically generating corresponding execute statements according to the input information of the user, completing corresponding execution operation aiming at a corresponding datasheet in the user database and obtaining an individualized database aiming at the user; and the common logic unit is used for calling corresponding user databases of various users aiming at the users, executing common logic, and providing the online individualized service for the user. The system can quickly adjust the prior product functions or develop new product functions to make a software system fully meet the individualized requirements of different users, and simultaneously can be continuously expanded and improved according to the development of user service to meet the continuously developed informatization requirement of the users.

A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.

The invention relates to a method and a device for generating a true random number. The device comprises a high frequency oscillator, an initial seed number generation unit, an error diffusion calculation unit, a linear feedback unit, a control unit and a random number output unit, wherein the output end of the high frequency oscillator is connected with the input end of the initial seed number generation unit; the output end of the initial seed number generation unit is connected with the input end of the error diffusion calculation unit; the output end of the error diffusion calculation unit is connected with the linear feedback unit; the output end of the linear feedback unit is connected with the control unit; and the control unit is connected with the random number output unit. The device achieves a metastable state circuit only by using general logic hardware, so the hardware structure is simplified; one-time-pad is realized by storing an initial seed number in a cache reset at each time; judgment and feedback control are realized by using a generator polynomial; and a secure hash algorithm is realized by using an error diffusion process, therefore, an effect that the random number is difficult to copy or forecast is achieved.

The invention provides a virtualization-based remote data recovery method and a virtualization-based remote data recovery device. The method comprises the following steps of: configuring a production disk and a copy disk; binding the production disk with the copy disk so as to form a common logic body and presenting the logic body in the form of a virtual disk; establishing the corresponding relation between the production disk and the physical memory position of the copy disk; redirecting the input and output of the virtual disk; after the virtual disk receives an initialization command, copying data of the production disk onto the copy disk according to the corresponding relation; after a data recovery command is received, copying data of the copy disk onto the production disk according to the corresponding relation; and after a data read-write command is received, performing data read-write operation according to a redirected read-write position. In the method, data can be used normally in a data recovery process and data security can be ensured.

This invention discloses a optimum design method for the finite field multiplier on the base of FPGA. This invention defines those logic functions which can be realized with a single 4-LUT into 7 styles, and it will follow some steps to realize the optimization for the finite field multiplier. Firstly, it figures out the matrix form of the finite field multiplier according to the generator polynomial and initialize the integration of middle variables. Secondly, it will repeatedly search for the common logic functions in the elements in the Matrix Z, bringing in a new middle variable, and it will use this new middle variable to represent the output variable of those logic functions, modifying the Matrix Z. Finally, it will find out preferred logic functions that can be realized by a single 4-LUT. Then those logic functions will be decomposed into a series of logic functions that can be realized by a single 4-LUT, and Matrix Z and the integration of middle variables will be modified. After all above, we finally get a optimized finite field multiplier on the base of FPGA. The advantages are short key route and time delay.

The present invention provides an optical disc with a generic logical format having a data structure that is defined independent of the content type (i.e., the data type and medium encoding scheme) and the physical medium. In accordance with one embodiment of the invention, a data storage medium is provided for storing data for access by a data processing system. The data storage medium comprises a data structure stored in the medium for describing different data contents stored therein. The data structure includes at least one content object containing data contents, an object definition file associated with the object for describing the object, and an index file including a table of contents having a reference to the object. The generic logical format of the invention can be easily adapted to any new content types without the need to define a complete new format.

The invention provides a digital control system, relates to the technical field of communication, and solves technical problems of enhancement of communication capacity and communication reliability. The system comprises a back board, and multiple generable logic cards and multiple signal backward-transmission modules which are interconnected with the backboard. All the general logic cards are divided into multiple logic card sequences, wherein one of the logic card sequences is an S sequence, and other logic card sequences are T sequences. In the T sequences, each general logic card is interconnected with all the general logic cards in the same sequence in a point-to-point communication mode and interconnected with the general logic cards of the corresponding positions in other T sequences in the point-to-point communication mode. In the S sequence, all the general logic cards are interconnected in the point-to-point communication mode, and each general logic card is interconnected with the general logic cards of the corresponding positions in all the T sequences in the point-to-point communication mode. The system is great in communication capacity and communication reliability.

Various embodiments provide methods and apparatus for implementing a microblog message page. An exemplary method can include encapsulating common logics of a plurality of message pages into a message page control base, pulling content data of a message page control of one message page of the plurality of message pages; and enabling the message page control of the one message page to inherit from the common logics encapsulated in the message page control base. The exemplary method can also include executing the common logics based on the pulled content data, to load the message page control of the one message page and to display the message page control on the one message page. The disclosed methods and apparatus can simplify the sorting algorithm with improved efficiency for the message pages to sort and manage layout of various types of controls.