The invention provides a finite field multiplier based on an RS (reed-solomon) code. The finite field multiplier based on the RS code is composed of two partial operations, firstly a common polynomial multiplication is carried out, and the obtained result is a polynomial with the highest order of 2m-2, wherein m is bit width of two finite field multipliers; and secondly, modular operation is carried out on the primitive polynomial p(x) by adopting the product polynomial, and the obtained remainder coefficient is namely final result of a finite field multiplication. The invention innovatively provides a two-step implementation method of the finite field multiplier. A modulus calculating circuit is composed of sublayers of the same structures, structure is regular, expansion is easy, engineering realization is applicable, the finite field multiplier with any bit width can be realized by regulating sublayers in a modulus obtaining circuit framework, and the finite field multiplier is especially applicable to error control code field such as application of the RS code and can meet urgent demand of easy implementation of VLSI (very large scale integration) design in a communication system.