Finite field multiplier based on RS (reed-solomon) code

Abstract

The invention provides a finite field multiplier based on an RS (reed-solomon) code. The finite field multiplier based on the RS code is composed of two partial operations, firstly a common polynomial multiplication is carried out, and the obtained result is a polynomial with the highest order of 2m-2, wherein m is bit width of two finite field multipliers; and secondly, modular operation is carried out on the primitive polynomial p(x) by adopting the product polynomial, and the obtained remainder coefficient is namely final result of a finite field multiplication. The invention innovatively provides a two-step implementation method of the finite field multiplier. A modulus calculating circuit is composed of sublayers of the same structures, structure is regular, expansion is easy, engineering realization is applicable, the finite field multiplier with any bit width can be realized by regulating sublayers in a modulus obtaining circuit framework, and the finite field multiplier is especially applicable to error control code field such as application of the RS code and can meet urgent demand of easy implementation of VLSI (very large scale integration) design in a communication system.

Description

technical field [0001] The invention relates to the field of error control codes and communication integrated circuits, in particular to a finite field multiplier based on RS codes. Background technique [0002] In data storage or digital communication systems, in order to reliably transmit or store digital information, certain redundant information must be added to the original information so that the receiving end can detect and correct errors. This is the so-called error correction coding . Reed-Solomon (Reed-Solomon, RS) code, as a non-binary BCH code, is widely used in digital communication, media storage and deep space communication because of its strong ability to correct random and burst errors. field. [0003] In the RS decoding process, the finite field multiplier is the most used unit. As the system has higher and higher requirements for error correction, the codec should be able to adapt to various applications and meet various specifications. These include th...

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Problems solved by technology

At present, the research on finite field multipliers based on RS codes has made some progress. Although some of the design schemes have reasonable design ideas, the circuits are complicated, and the irregular communication and cumbersome control between components make them unsuitable for VLSI design.

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