43results about How to "Reduce saturation pressure drop" patented technology

The invention discloses a Schottky barrier high-current-density IGBT device comprising a P type base region, a poly silicon gate region, a N- type doped drift region in contact with the bottom surface of the P-type base region, a first device in contact with the bottom surface of the N- type doped drift region, a Schottky barrier region, a N+ type doped source region, an emitter metallic region, and a gate oxide layer. The Schottky barrier region and the N+ type doped source region are in contact with the top surface of the P type base region. The emitter metallic region is in contact with the Schottky barrier region and the N+ type doped source region. The emitter metallic region is arranged between the poly silicon gate region and a group including the N- type doped drift region, the P type base region, the N+ type doped source region, and the emitter metallic region. While advantages of high operating voltage, simple gate voltage control, good switching controllability, a safe operating area, and simple short circuit protection measures are maintained, the Schottky barrier high-current-density IGBT device is greatly increased in current density, improved in conductivity modulation effect and current conduction capability, and decreased in on-state loss.

The invention relates to a suspension collector PNP integrated circuit transistor and a manufacturing method thereof. An N-type first epitaxial layer and an N-type second epitaxial layer are sequentially formed on a P-type substrate; an N-type buried layer is arranged in the P-type substrate, a collector P-type buried layer is arranged in the first epitaxial layer which is positioned on the N-type buried layer, and a collector upper isolation unit is arranged in the second epitaxial layer which is positioned on the collector P-type buried layer; a P-type lower isolation unit is arranged in the first epitaxial layer which is positioned on the upper portion of the periphery of the N-type buried layer, and a P-type upper isolation unit is arranged in the second epitaxial layer which is positioned on the P-type lower isolation unit; a first P+ diffusion region is arranged in the P-type upper isolation unit, and serves as a collector; an N+ diffusion region is arranged in the second epitaxial layer enclosed by the collector upper isolation unit and the collector P-type buried layer, and serves as a base; and a second P+ diffusion region is arranged in the second epitaxial layer enclosed by the N+ diffusion region, and serves as an emitter. The suspension collector PNP integrated circuit transistor and the manufacturing method thereof can reduce collector series resistance and saturation voltage drop, and increase current output capacity.

The invention discloses a power transistor manufacture method. By the method, insulating medium layers formed on the top of gate polycrystalline silicon and spacer medium layers formed on the side faces of the insulating medium layers serve as hard masks for etching a pressure-bearing region, so that the number of masks required by the front-side process is decreased, and the density of transistors in a chip can be increased. By the aid of the method, a trench is formed in a P-type well region by etching, and a P-type polycrystalline silicon layer and an N-type polycrystalline silicon layer are filled inside the trench and subjected to annealing to promote formation of a source electrode and a back gate contact region which are longitudinally distributed, so that latching resistance of devices can be improved, and power devices lower in breakover resistance and saturation voltage drop and higher in current driving capacity can be obtained beneficially.

The invention provides an insulated gate bipolar transistor and a manufacturing method thereof. The manufacturing method of the insulated gate bipolar transistor includes: providing a substrate, the substrate having a cell region and a dummy cell region; forming A gate structure is in the substrate, and the gate structure separates the cell region from the dummy cell region; and, high-energy ion implantation is used to form a well region in the substrate of the dummy cell region , so that a PN junction is formed between the well region and the substrate, and the top surface of the well region is lower than the top surface of the substrate and not lower than the bottom surface of the gate structure. The technical scheme of the invention can accurately control the junction depth of the PN junction in the virtual cell area, thereby improving the withstand voltage of the device, reducing the saturation voltage drop of the device, and improving the stability and uniformity of the threshold voltage.

The invention discloses a direct-current overvoltage protection circuit. The direct-current overvoltage protection circuit comprises an input filter circuit, an overvoltage detection circuit, a variable impedance electronic switch drive circuit, a variable impedance electronic switch circuit, a voltage stabilizing circuit, a reduced saturation voltage drop circuit, an output filter voltage stabilizing circuit and a load, wherein the input end of the input filter circuit is connected with an input signal; the output end of the input filter circuit is respectively connected with the overvoltage detection circuit and the reduced saturation voltage drop circuit; the output of the overvoltage detection circuit is connected with the variable impedance electronic switch drive circuit; the output of the variable impedance electronic switch drive circuit is connected with the variable impedance electronic switch circuit; the output of the variable impedance electronic switch circuit is connected with the voltage stabilizing circuit; the output of the voltage stabilizing circuit is connected with the reduced saturation voltage drop circuit; the output of the reduced saturation voltage drop circuit is connected with the output filter voltage stabilizing circuit; and the output of the output filter voltage stabilizing circuit is connected with the load.

The invention provides a field stop buffer layer which is formed in an IGBT (Insulated Gate Bipolar Transistor) device. The field stop buffer layer comprises an N type substrate and a P type buried layer formed in the N type substrate. The invention also provides an IGBT device with the field stop buffer region. The IGBT device comprises the field stop buffer layer, an N-epitaxial layer, an IGBT front structure, an anode cavity emission region and a back anode collector electrode, wherein the field stop buffer layer comprises the N type substrate and the P type buried layer formed in the N type substrate; the N-epitaxial layer is formed on the surface of the N type substrate; the IGBT front structure is formed on the surface of the N-epitaxial layer; the anode cavity emission region is formed on the back surface, which is far away from the N-epitaxial layer, of the N type substrate; and the back anode collector electrode is formed on the anode cavity emission region. The invention also provides a manufacture method of the IGBT device with the field stop buffer layer. Through increasing the thickness of the field stop buffer layer and regulating the concentration and the thickness between the P type buried layer and the N type substrate, the current density of the IGBT device is increased, and the conduction loss is reduced.

The invention relates to an IGBT device with a carrier storage structure and a manufacturing method thereof. An active area of the IGBT device adopts a groove structure; a second conduction type body area is arranged in a first conduction type drifting area of the active area; a cellular groove is located in the second conduction type body area and deeply extends into the first conduction type drifting area below the second conduction type body area; the carrier storage structure is arranged in the first conduction type drifting area of the active area; the carrier storage structure comprises a first conduction type carrier storage area which is used for completely surrounding the inner and outer walls, extending in the first conduction type drifting area, of the cellular groove; and the doping concentration of the first conduction type carrier storage area is greater than the doping concentration of the first conduction type drifting area. According to the IGBT device with the carrier storage structure and the manufacturing method thereof, the relatively low breakover voltage drop and extremely rapid turnoff characteristic can be satisfied at the same time, the pressurization breakdown position can be adjusted to a cellular area to ensure relatively high voltage surge resistance, the chip manufacturing cost is not increased, and the chip area is reduced.