A method for manufacturing a silicon epitaxial wafer of a high-power pin device
A technology of silicon epitaxial wafers and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of reducing the effective thickness of the epitaxial layer, low edge resistivity, uneven breakdown voltage and series resistance, etc. , to achieve the effect of reducing gas phase self-doping, ensuring performance and yield, and reducing the transition zone width
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[0012] The present invention is described in detail below by specific embodiment:
[0013] The method for manufacturing silicon epitaxial wafers for PIN tubes in this embodiment uses N-type polished wafers heavily doped with As, with resistivity ≤ 0.003 Ω·cm, local flatness ≤ 1.5 mm, and no back-sealing oxide layer on the back. The process is as follows: 1. Use the principle of mass transfer to transfer polysilicon from the graphite base to the back of the substrate to achieve the purpose of back encapsulation; 2. Select the appropriate gas corrosion flow rate and gas corrosion time to reduce the gas corrosion impurities in the epitaxial reaction chamber 3. After gas corrosion, choose hydrogen with variable temperature and flow rate to purge the epitaxial reaction chamber to reduce the impurity concentration in it; 4. The first layer of epitaxial growth: at high The surface of the substrate with a lower temperature is used to grow an intrinsic epitaxial layer for encapsulatio...
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