Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for growing thin-layer high-resistance silicon epitaxial wafer and prepared epitaxial wafer

A technology for epitaxial wafers and high-resistance silicon, applied in crystal growth, single crystal growth, single crystal growth, etc., can solve problems such as increased epitaxy costs, surface quality of epitaxy defects, and increased influence of system self-doping, so as to suppress impurity diffusion and evaporation, reducing solid-state diffusion and gas-phase self-doping, and reducing the effect of system self-doping

Inactive Publication Date: 2021-08-31
NANJING GUOSHENG ELECTRONICS
View PDF11 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, when growing a thin layer of high-resistance silicon epitaxial layer on a heavily doped substrate, in addition to the influence of substrate self-doping and solid-state out-diffusion, the influence of system self-doping in the reaction chamber is also significantly increased.
In order to reduce self-doping and improve the longitudinal carrier concentration distribution of the epitaxial layer, the main methods currently include low-temperature growth, high-temperature baking, variable-speed growth, and two-step epitaxy, etc., but they cannot effectively solve the problem of substrate self-doping in thin-layer high-resistance epitaxy. Doping and system self-doping problems, and too low growth temperature will cause epitaxial defects and surface quality problems, high temperature baking and variable speed growth will increase the cost of epitaxy

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for growing thin-layer high-resistance silicon epitaxial wafer and prepared epitaxial wafer
  • Method for growing thin-layer high-resistance silicon epitaxial wafer and prepared epitaxial wafer
  • Method for growing thin-layer high-resistance silicon epitaxial wafer and prepared epitaxial wafer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0027] A method for growing a thin-layer high-resistance silicon epitaxial wafer on a heavily doped As substrate, comprising the following steps:

[0028] (1) Use high-flow HCL to clean the reaction chamber and graphite base before loading to remove reaction residues.

[0029] (2) As-doped substrate is selected, and the resistivity is 0.001~0.004Ω.cm; the back of the substrate is sealed with silicon dioxide, and the edge width of the back-sealing layer is only removed from the chamfered surface.

[0030] (3) To grow the first epitaxial layer, set the pressure of the reaction chamber to 30Torr, grow the first epitaxial layer on the surface of the substrate with a growth temperature of 1080°C and a growth rate of 0.7 μm / min, and the first epitaxial layer cannot pass dopants gas. A pure epitaxial layer is grown on the surface of the substrate with a low growth temperature and a low growth rate, and the growth temperature, growth rate and epitaxy time are controlled to effectivel...

Embodiment 2

[0036] A method for growing a thin-layer high-resistance silicon epitaxial wafer on a heavily doped As substrate, comprising the following steps:

[0037] (1) Use high-flow HCL to clean the reaction chamber and graphite base before loading to remove reaction residues.

[0038] (2) As-doped substrate is selected, and the resistivity is 0.001~0.004Ω.cm; the back of the substrate is sealed with silicon dioxide, and the edge width of the back-sealing layer is only removed from the chamfered surface.

[0039] (3) Carry out the growth of the first epitaxial layer, set the pressure of the reaction chamber to 10Torr, grow the first epitaxial layer on the substrate surface with a growth temperature of 1050°C, and a growth rate of 0.5 μm / min, and the first epitaxial layer cannot pass dopants gas. A pure epitaxial layer is grown on the surface of the substrate with a low growth temperature and a low growth rate, and the growth temperature, growth rate and epitaxy time are controlled to ...

Embodiment 3

[0045] A method for growing a thin-layer high-resistance silicon epitaxial wafer on a heavily doped As substrate, comprising the following steps:

[0046] (1) Use high-flow HCL to clean the reaction chamber and graphite base before loading to remove reaction residues.

[0047] (2) As-doped substrate is selected, and the resistivity is 0.001~0.004Ω.cm; the back of the substrate is sealed with silicon dioxide, and the edge width of the back-sealing layer is only removed from the chamfered surface.

[0048](3) To grow the first epitaxial layer, set the pressure of the reaction chamber to 50Torr, grow the first epitaxial layer on the substrate surface with a growth temperature of 1100°C, and a growth rate of 1.0 μm / min, and the first epitaxial layer cannot pass dopants gas. A pure epitaxial layer is grown on the surface of the substrate with a low growth temperature and a low growth rate, and the growth temperature, growth rate and epitaxy time are controlled to effectively encap...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
electrical resistivityaaaaaaaaaa
evennessaaaaaaaaaa
evennessaaaaaaaaaa
Login to View More

Abstract

The invention discloses a method for growing a thin-layer high-resistance silicon epitaxial wafer. The method comprises the following steps: preparing a substrate slice: selecting an As-doped substrate; setting the pressure intensity of the reaction cavity to be 10-50 Torr, setting the growth temperature of the surface of the substrate to be 1050-1100 DEG C, and adopting dichlorosilane (DCS) as a silicon source to grow a first epitaxial layer; and setting the pressure intensity of a reaction cavity to be 10-80 Torr, and growing a second epitaxial layer on the first epitaxial layer at the growth temperature of 1050-1100 DEG C by adopting dichlorosilane (DCS) as a silicon source. According to the method, impurity diffusion and evaporation of the heavily-doped As substrate can be inhibited, solid diffusion and gas phase self-doping can be reduced, narrow transition region width, high epitaxial resistivity and uniform epitaxial resistivity distribution can be obtained under the condition of thin epitaxial thickness, the breakdown voltage of the device is ensured, and the on resistance of the device is also considered.

Description

technical field [0001] The invention relates to a method for manufacturing an epitaxial wafer, in particular to a method for growing a thin-layer high-resistance silicon epitaxial wafer on a heavily doped As substrate. Background technique [0002] With the rapid rise of emerging industries such as smart home, automotive electronics, artificial intelligence, new energy, and the Internet of Things, the semiconductor discrete device industry has ushered in a new round of development. Photodetector diodes, PIN diodes, high-speed varactor diodes, high-speed Discrete transistors are important components, and the demand for thin-layer high-resistance silicon epitaxial materials used in them is increasing day by day. [0003] However, growing a thin layer of high-resistance silicon epitaxial layer on a heavily doped substrate is not only affected by the substrate self-doping and solid-state out-diffusion, but also the system self-doping effect of the reaction chamber is also signif...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): C30B25/14C30B25/16C30B29/06C30B31/16C30B31/18H01L21/02
CPCC30B25/14C30B25/16C30B29/06C30B31/16C30B31/18H01L21/02381H01L21/02532H01L21/0262
Inventor 马梦杰王银海邓雪华杨帆
Owner NANJING GUOSHENG ELECTRONICS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com