457results about How to "Increase cell density" patented technology

A memory cell for magnetic random access memory devices based on a magnetic tunnel junction (MTJ) memory element with a perpendicular orientation of magnetization in pinned and free magnetic layers, and a tunnel barrier layer sandwiched between the pinned and free layers. The memory cell can include the MTJ memory element, a magnetic flux guide in series with selection devices, such as a bit line, a word line, and a transistor. The magnetic flux guide can have two electrically conductive magnetic portions with the MTJ memory element positioned between the magnetic portions. The MTJ memory element is magnetically isolated from the magnetic flux guide by thin non-magnetic conductive spacers. The MTJ memory element is arranged in a vertical space between the intersecting bit and word lines at their intersection region. The memory cell also includes write and excitation lines. The write line is parallel to the bit line and the excitation line is parallel to the word line. The write and excitation lines also intersect each other and define a corner. The MTJ memory element is positioned in the corner of the intercepting write and excitation lines.

The present invention provides an improved expression system for the production of recombinant polypeptides utilizing auxotrophic selectable markers. In addition, the present invention provides improved recombinant protein production in host cells through the improved regulation of expression.

Recombinant microorganisms and related methods of use to enhance tolerance to toxic substances. In particular, such microorganisms and methods can be used to increase solvent production.

The invention discloses a polypropylene foaming material. The polypropylene foaming material comprises the following components according to proportioning by weight: 60-99 parts of polypropylene resin; 0.1-10 parts of nucleating agent; 0.1-5 parts of antioxidant; 0-5 parts of colorant; 0-5 parts of lubricant; and 0-20 parts of filling material; and the melt index of the polypropylene resin is 0.1-20 g / 10 min, and the foaming process adopts supercritical fluid as the foaming agent, i.e. 0.1-20 parts of supercritical fluid (proportioning by weight). The invention also discloses a production method of the foaming material. Compared with the prior art, the invention has the advantages that the universal polypropylene can be adopted as a base material, no polymer is provided, the cross-linking reaction does not occur, the foaming process is free from environmental pollution, and the production method is safe; the quality of the obtained foaming material is stable, the foaming percentage and the cell density are high, the distribution is uniform, and the invention is suitable for the industrial production at a large scale; and meanwhile, the overall production method is simple, the operation is easy, and the production cost is relatively lower.

The present invention discloses a three-dimensional porous growth surface made from polysaccharide material, especially the alginic acid, to enhance cell growth surface, promote cell adherence, immobilization and propagation, maintain surface structure integrity, enable programmable degradation, and thus increase cellular production. The present invention teaches several methods: a method to enhance the integrity of the growth surface by protecting the growth surface in a rigid solid support; a method of use for enhancing the performance of the surface; and a method of modifying a growth surface for eukaryotic and / or prokaryotic cells comprising the steps of increasing surface area by creating porous and 3-D structure, treating a surface to encourage cell attachment, promoting cell growth and proliferation, and disposing the growth surface in any conventional cell cultivating device. The growth surface is able to program degradation and release the cell / tissue mass after the culture is completed.

A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the higher band gap energy of silicon carbide as compared to silicon. The silicon carbide provides much lower thermally dependent leakage currents which enables significantly longer refresh intervals. In certain applications, the cell is effectively non-volatile provided appropriate gate bias is maintained. N-type source and drain regions are provided along with a pillar vertically extending from a substrate, which are both p-type doped. A floating body region is defined in the pillar which serves as the body of an access transistor as well as a body storage capacitor. The cell provides high volumetric efficiency with corresponding high cell density as well as relatively fast read times.

A semiconductor power device supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

The present invention provides a method of increasing protein production in a cell culture by growing cells that produce the protein (e.g., the growth phase) in a perfusion cell culture to a high cell density (i.e., at least above about 40×106 cells / N mL) and then switching to a protein production phase, wherein the cells are cultured in a fed-batch cell culture. The present invention further provides a method for clarifying a protein from a cell culture by adjusting the pH of the cell culture to below neutral pH (i.e., below a pH of 7) and settling the cell culture, such that the cell culture separates to form a supernatant layer and a cell-bed layer, wherein the protein is in the supernatant layer.

A hybrid semiconductor power device that includes a plurality of closed power transistor cells each surrounded by a first and second trenched gates constituting substantially a closed cell and a plurality of stripe cells comprising two substantially parallel trenched gates constituting substantially an elongated stripe cell wherein the closed cells and stripe cells constituting neighboring cells sharing trenched gates disposed thereinbetween as common boundary trenched gates. The closed MOSFET cell further includes a source contact disposed substantially at a center portion of the closed cell wherein the trenched gates are maintained a critical distance (CD) away from the source contact.

A trench MOSFET with on-resistance reduction comprises a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate, wherein the said MOSFET further comprises a plurality of source-body contact trenches opened relative to a top surface into said source and body regions and each of the source-body contact trenches is filled with a contact metal plug as a source-body contact; a insulation layer covered over the top of the trenched gate, the body region and the source region; a front metal layer formed on a top surface of the MOSFET; wherein a low-resistivity phosphorus substrate and retrograded P-body formed by medium or high energy Ion Implantation to reduce Rds contribution from substrate and drift region.

A semiconductor power device is supported on a semiconductor substrate with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

A memory cell for use in a magnetic random access memory (MRAM) circuit includes at least first and second transistors formed in a semiconductor layer. A first insulating layer is formed on at least a portion of the first and second transistors. The memory cell further includes a first magnetic storage element formed on at least a portion of the first insulating layer, at least a second insulating layer formed on at least a portion of the first magnetic storage element, and at least a second magnetic storage element formed on at least a portion of the second insulating layer. The first and second magnetic storage elements are electrically connected to the first and second transistors, respectively.

Voltage controlled magnetic tunnel junctions and memory devices are described which provide efficient high speed switching of non-volatile magnetic devices at high cell densities. Implementations are described which provide a wide range of voltage control alternatives with in-plane and perpendicular magnetization, bidirectionally switched magnetization, and control of domain wall dynamics.

A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

A trench-gated MOSFET formed using a super self aligned (SSA) process employs an insulating layer such as a glass layer and a contact mask to define contact openings for electrical connections to source regions of the MOSFET. Use a contact mask and an intervening glass in otherwise self-aligned process reduces the coupling capacitance between source metal and the top of the embedded trench gate. A metal layer deposited to make electrical contact to source regions can be planarized, for example, ground flat using chemical-mechanical polishing to provide a flat surface to avoid formation of conductive traces that extend over the steps that the glass layer forms.

A trench MOSFET device comprising: (a) a silicon substrate of a first conductivity type (preferably N-type conductivity); (b) a silicon epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a body region of a second conductivity type (preferably P-type conductivity) within an upper portion of the epitaxial layer; (d) a trench having trench sidewalls and a trench bottom, which extends into the epitaxial layer from an upper surface of the epitaxial layer and through the body region of the device; (f) an oxide region lining the trench, which comprises a lower segment covering at least the trench bottom and upper segments covering at least upper regions of the trench sidewalls; (g) a conductive region within the trench adjacent the oxide region; and (h) a source region of the first conductivity type within an upper portion of the body region and adjacent the trench. The lower segment of the oxide region is thicker than the upper segments of the oxide region in this embodiment.

The invention disclosed provides a method for inducing nucleation in a polymer by subjecting the polymer containing dissolved gas to an external stress generated, for example, by applying hydrostatic or mechanical pressure. The applied stress restricts the bubble growth so that the foamed materials have small cells and high cell density. Such microcellular foams can be produced over a wide low temperature range, i.e. from the temperature at which the polymer is conditioned with the blowing agent up to about the glass transition temperature of the polymer-blowing agent system. Stress induced nucleation can also be conducted at higher temperatures i.e. up to about the Tg of the neat polymer, leading to foams with larger cells. A variety of homogeneous and heterogeneous foams can be produced by this technique.

A memory cell field with an integrated arrangement of solid body electrolyte memory cells, and in particular of CBRAM solid body electrolyte memory cells with 1T1R architecture, wherein the solid body electrolyte memory cells each comprise a layer stack that comprises at least a bottom and a top electroconductive, in particular metal layer and a layer of solid body electrolyte material or ion conductor material, respectively, positioned therebetween, and wherein each solid body electrolyte memory cell can be controlled via a word line, a bit line, and a plate line by means of a selection transistor, wherein at least a number of solid body electrolyte memory cells in the memory cell field have a common plate electrode or are connected to a common plate line, respectively.

The present invention relates to a catalyst (1) for combustion of at least a portion of a gaseous fuel-oxidant mixture flowing through the catalyst (1), in particular for a burner of a power plant. An inlet sector (5) comprises inlet channels (9). A succeeding sector (6) comprises succeeding channels (10). The succeeding channels (10) have smaller internal cross-sectional areas than the inlet channels (9). To improve the production of the catalyst (1), the invention proposes channels (3) which extend through the inlet sector (5) and through the succeeding sector (6) and have the internal cross-sectional area of the inlet channels (9). The inlet channels (9) are formed by portions of the channels (3) lying in the inlet sector (5). The succeeding channels (10) are provided by arranging separation walls (11) within portions of the channels (3) lying in the succeeding sector (6), the separation walls (11) dividing each of the respective channel portions in the succeeding sector (6) into two succeeding channels (10).

A trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source-body contact trench opened with sidewalls substantially extend vertically relative to a top surface into the source and body regions and filled with contact metal plug. A body-resistance reduction region doped with body-doped is formed to surround the source-body contact trench to reduce a body-region resistance between the source-body contact metal and the trenched gate to improve an avalanche capability.