53results about How to "Optimizing place and route" patented technology

The invention relates to a centralized-cache device and design method based on field-programmable gate arrays and relates to the field of field-programmable gate array design, and the centralized-cache device and design method is adaptive to at least two same functional modules. The device comprises a time division multiplexing control unit, a signal serialization unit, a centralizing storage register, a combinational logic unit and a signal parallelization unit. The time division multiplexing control unit is used for dividing the period into two time slots with the same length of time, each time slot corresponds to one functional module sequentially, and each functional module performs input signal processing in the corresponded time slot. The signal serialization unit is used for converting the parallel input signals of each functional module into serial input signals. The centralizing storage register is used for storing the register of each functional module and reading and writing the register of the functional module in the time slot corresponding to the functional module. The combinational logic unit is used for combinational logic of input signal processing of single functional module. The signal parallelization unit is used for restoring serial output signals as parallel output signals after the input signals of each functional module are processed.

The application discloses a synchronous FIFO, which includes a data storage circuit, a first logic circuit, a second logic circuit and an indication circuit. The data storage circuit includes N first registers, N first multiplexers and N first decision devices; N is a positive integer; the first registers are alternately connected to the first multiplexers. The synchronous FIFO is based on registers to build the storage required for FIFO, mainly including registers, multiplexers, and decision devices. RAM is discarded, no RAM is occupied, no RAM read and write enable and address control are required, and RAM resource waste can be avoided. It occupies less resources in the design with less memory depth requirements, greatly reduces the chip area, saves cost, and is more convenient for layout and wiring.

The invention discloses a routing method based on hierarchical Q-routing planning, which is to obtain high-efficiency data transmission links through global layered parallel planning by sensing network congestion and interconnection link usage. The algorithm of the present invention is a routing algorithm based on a lookup table. The routing algorithm stores the planned direction in the routing table in the learning module of each router node, and the data packet is obtained by accessing the routing table in the learning module of the router node. path information. The present invention constructs a hierarchical design on the basis of split Q-routing, utilizes multi-layer congestion sensor and multi-layer parallel learning to greatly reduce the convergence time of the algorithm, thereby improving the data transmission efficiency of the on-chip network, and also compressing the routing table , reducing hardware resource consumption.