System on chip and resting and arousing method thereof

Abstract

The invention relates to the technical field of a system on a chip and discloses a system on a chip and a resting and arousing method thereof. In the system on the chip, a main voltage area and an auxiliary voltage area are designed, the auxiliary voltage area in which a micro-control unit is arranged can be closed or stepped down, information in the auxiliary voltage area is stored into a memory in the main voltage area by the micro-control unit before the auxiliary voltage area is powered down, the dynamic power consumption and the static power consumption of a digital circuit can be lowered, and the condition that the necessary information can not be lost can also be ensured; and moreover, the system on the chip does not need to depend on the support of a specific process or a specific component, which is very beneficial to arranging and wiring. After the system on the chip is aroused, the auxiliary voltage area is at a resetting state, and the occurrence of confusion of the working of a circuit is avoided; and until the voltage of the auxiliary voltage area is restored to a normal value, the auxiliary voltage area is released and reset, so that the entire circuit is in normal working anew.

Description

technical field [0001] The invention relates to the technical field of a system on a chip, in particular to a system on a chip low power consumption power switch and its sleep and wake-up technology. Background technique [0002] In the field of System On Chip ("SOC" for short), low power consumption technology has always been a hot spot. In general SOC low power consumption design, clock gating or power gating is adopted. Gating) method for power consumption control. [0003] Clock Gating technology is to reduce power consumption by turning off the digital circuit clock. The basic idea of ​​clock gating is to turn off the clock when the register is not working (when the enable signal is invalid), so that the buffers and registers on the clock tree will no longer have dynamic power consumption. The disadvantage of this method of reducing power consumption is that although the dynamic power consumption is reduced, the static power consumption of complementary metal oxide se...

AI Technical Summary

Problems solved by technology

The inventors of the present invention have found that simple ClockGating and Power Gating technologies cannot completely solve the power consumption problem of electric energy metering chips

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