Centralized cache device and design method based on field programmable gate array

Abstract

The invention relates to a centralized-cache device and design method based on field-programmable gate arrays and relates to the field of field-programmable gate array design, and the centralized-cache device and design method is adaptive to at least two same functional modules. The device comprises a time division multiplexing control unit, a signal serialization unit, a centralizing storage register, a combinational logic unit and a signal parallelization unit. The time division multiplexing control unit is used for dividing the period into two time slots with the same length of time, each time slot corresponds to one functional module sequentially, and each functional module performs input signal processing in the corresponded time slot. The signal serialization unit is used for converting the parallel input signals of each functional module into serial input signals. The centralizing storage register is used for storing the register of each functional module and reading and writing the register of the functional module in the time slot corresponding to the functional module. The combinational logic unit is used for combinational logic of input signal processing of single functional module. The signal parallelization unit is used for restoring serial output signals as parallel output signals after the input signals of each functional module are processed.

Description

technical field [0001] The invention relates to the field of field programmable gate array design, in particular to a centralized cache device and design method based on field programmable gate array. Background technique [0002] FPGA (Field Programmable Gate Array, field programmable gate array) is in PAL (Programmable Array Logic, programmable array logic), GAL (Generic Array Logic, general array logic), PLD (Programmable Logic Device, programmable logic device), etc. The product of further development on the basis of programmable devices is the most integrated ASIC (Application Specific Integrated Circuit, application specific integrated circuit). The programmable feature of FPGA makes this device uniquely flexible, which can help system manufacturers launch products and realize industrialization in the shortest time; with the advancement of technology, the NRE (Non-Recurring Engineering, one-time Sexual engineering) costs are getting higher and higher, and traditional ...

AI Technical Summary

Problems solved by technology

[0004] When the FPGA design contains N identical functional modules, the usual implementation method is to complete a functional module and then make N copies, such as figure 1 As shown, if a functional module occupies X combinational logic units, Y registers, and Z internal connections, then after N times of duplication, it will generally occupy X×N combinational logic units, Y×N registers, and Z×N There are only one internal connection, which seriously consumes the hardware resources of the FPGA and increases the design cost. At the same time, too many internal connections may also cause the maximum frequency (Fmax) that the entire design can achieve to fail to meet the requirements.

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