43results about How to "Save wiring resources" patented technology

A leakage current control circuit with a single low voltage power supply is provided. The circuit includes a first power supply line, a second power supply line, a ground line, a high voltage generating circuit, a power transistor and a control circuit. The high voltage generating circuit generates a voltage in response to an internal sleep signal. The gate electrode of the power transistor is connected to the output of the high-voltage generating circuit such that the power transistor is controlled by the high voltage generating circuit. When the power transistor turns on, the circuit is in operation mode; when the power transistor is off, the circuit is in sleep mode. The control circuit connects to the first power line, the second power line, and the ground line to output the internal sleep signal in response to the sleep signal.

This invention provides a device for taking a two- dimensional fast DCT transform or a two -dimensional fast IDCT transform to the image data composed of 8X8 sub-block. Takes example for one dimensional DCT transform to 8X8 sub-block: the transform device comprises: the control circuit; the input deposit circuit; the butterfly operation circuit; the parallel / serial conversion circuit; table look up operation circuit; the output deposit circuit. The invention adopts the design philosophy that is to replace the multiply operation by look up table, so it need only once butterfly operation, 24 adder, 0 multiplying to complete once DCT. The design philosophy using the pipeline greatly increases the operating speed. The data can be inputted consecutively, the operation result can be gotten at each clock period. The invention is adapted to implement by using FPGA, the resource requirement saves above 30% than current structure. It can be applied in various image compression, especially in MPEG, H.26X format data that makes high requirement for the compression speed and quality.

The invention relates to a surge current control module, which is used in an integrated circuit chip. The integrated circuit chip comprises a plurality of function units and M corresponding power switches for controlling power supplies of the function units to switch on or off; the surge current control module comprises a programmable counter unit, a selector unit and an enable signal drive circuit module; a surge current control method comprises the steps that the M power switches are divided into N groups and are connected with N groups of enable signal drive circuits; the selector unit is provided with N groups of output ends, which output N groups of enable signal En to the N groups of enable signal drive circuits; the programmable counter unit controls the selector unit to output on-off signals to the N groups of power switches according to a certain preset time at intervals through setting count capacity, and switching on the M power switches which are divided into N groups by adopting time interval echelon so as to reduce the transient surge current. Therefore, the reliability of the chip can be improved, and the manufacturing cost of the chip is reduced.

The invention relates to a algorithm for designing a power supply network quickly. In the algorithm, based on the guarantee for meeting chip power consumption requirement, power supply strips conducting small currents in a uniform power supply network are removed and thus a non-uniform power supply network is formed for optimizing the power supply network after arrangement, and wire laying resources are saved as much as possible while the power supply requirement of a chip is met. Compared with the conventional design scheme, the algorithm for designing the power supply network saves wire laying resources and obviously reduces design iteration time.

Provided is a semiconductor device having staggered pad arrangement wherein pads are arranged by being alternately shifted, as a pad arrangement for connecting with an external package on an LSI. In the semiconductor device, wire short-circuit during assembly, chip size increase due to wire short-circuit prevention, propagation of power supply and GND noise due to reduction of an IO cell interval, signal transmission delay difference due to pad position shift, and the like can be eliminated. In the semiconductor device, a plurality of pads to be connected with functional terminals of the external package on the semiconductor element are arranged in two rows along the periphery of the semiconductor element. The arrangement order of the pads on the semiconductor element is different from that of the functional terminals of the external package.

The invention relates to a method for packing and deploying adders. The method includes the steps of: identifying the design mode of the adders and other packageable modules in a design of a user; then packing the adders and other packageable modules into one macro block; and disposing the macro block in a logic unit with a fast physical connection line. According to the invention, the design mode of the user can be matched through a usage mode according to the inherent fast line resource of a chip; and after the design mode of the user is matched, the line routing resources used by the adders and other modules are reduced, thereby reducing usage of line routing resources and also reducing the time delay.

The invention relates to a centralized-cache device and design method based on field-programmable gate arrays and relates to the field of field-programmable gate array design, and the centralized-cache device and design method is adaptive to at least two same functional modules. The device comprises a time division multiplexing control unit, a signal serialization unit, a centralizing storage register, a combinational logic unit and a signal parallelization unit. The time division multiplexing control unit is used for dividing the period into two time slots with the same length of time, each time slot corresponds to one functional module sequentially, and each functional module performs input signal processing in the corresponded time slot. The signal serialization unit is used for converting the parallel input signals of each functional module into serial input signals. The centralizing storage register is used for storing the register of each functional module and reading and writing the register of the functional module in the time slot corresponding to the functional module. The combinational logic unit is used for combinational logic of input signal processing of single functional module. The signal parallelization unit is used for restoring serial output signals as parallel output signals after the input signals of each functional module are processed.

The invention relates to an artificial neural network hardware implementation device based on probability calculation. The artificial neural network hardware implementation device based on probability calculation comprises input, intermediate and output modules. The input module is formed by I input neurons, and the input neurons receive first data and output a first random data sequence; the intermediate module is formed by J intermediate neurons, and the intermediate neurons receive the first random data / parameter sequence and output a second random sequence; and the output module is formed by K output neurons, and the output neurons receive the second random data / parameter sequence and output the second data, wherein I, J and K are integers greater than or equal to 1. The output end of the input neurons is connected with the input end of the intermediate neurons, the output end of the intermediate neurons is connected with the input end of the output neurons, and a complete or partial connection mode is adopted. The first and second random data sequences and the first and second random parameter sequences are expressed by the probability values of 0 or 1 appearing in the data sequences within a period of time. According to the neural network device, hardware logic and wiring resources can be greatly reduced, and circuit cost and power consumption can be reduced so that implementation of a super-large-scale neural network through small and medium-sized circuits is enabled to be possible.

The invention provides a signal transmission method, a signal transmission device and a signal receiving device. The method comprises the steps of carrying out parallel-to-serial conversion processing on m parallel module switching control signals according to clock signals of which carrier frequency is multiplied by p and carrier signals with equal duty cycles, thereby obtaining n serial module switching control signals; carrying out drive processing on the clock signals of which carrier frequency is multiplied by p and the carrier signals with the equal duty cycles, thereby generating n clock signals of which carrier frequency is multiplied by p and n carrier signals with the equal duty cycles; and sending the n serial module switching control signals, the n clock signals of which carrier frequency is multiplied by p and the n carrier signals with the equal duty cycles to a signal receiving device, wherein the m is equal to n*p, the m is greater than 1 and is smaller than or equal to 224 and the m is a positive integer, the n is greater than 1 and is smaller than or equal to 28 and the n is the positive integer, and the p is the positive integer. A great number of wiring resources are reduced, and the same frequency interference between the carrier signals and the module switching control signals is reduced.

Provided are a test substrate and a probe card manufactured using the test substrate. Test-end micro bulges (2) on a top surface of the test substrate are arranged according to the layout of contacts (7) to be detected at the bottom of a wafer (10) to be detected, are correspondingly connected to through-substrate via holes (3) via top wirings (8) and are electrically conducted, the through-substrate via holes (3) are correspondingly connected to detection bulges (4) on the bottom surface of the test substrate and are electrically conducted, and the detection bulges (4) match test probes (13) in size, so that a one-to-one correspondence signal relationship between the test probes (13) and the test-end micro bulges (2) and the contacts (7) to be detected is established, and the problem that there is no way for the test probes (13) to directly detect each contact (7) to be detected due to the test probes (13) being too big and the contacts (7) to be detected being too small in the related art is solved. By overlaying an anisotropic conductive resin on the top surface of the test substrate, the test-end micro bulges (2) can be electrically conducted without the need for them to come into contact with the contacts (7) to be detected, thereby avoiding damage to the wafer (10) and improving the signal transmission property.

The embodiment of the invention discloses an Ethernet service transmitting and receiving method and device capable of dynamically configuring a bandwidth, which are used for the field of information transmission; an Ethernet data frame is scrambled into a high-definition image HD-SDI signal after being encoded; the Ethernet service is enabled and decoded to seamlessly fuse two service data of a HD-SDI (High-Definition Serial Digital Interface) image signal and Ethernet data on an HD-SDI; without substantially affecting the image quality, the bandwidth is dynamically configured to transmit the Ethernet service data while the HD-SDI image signal is transmitted; meanwhile, absolute isolation is assured at two levels of the high-definition image signal and the Ethernet service data so that the mutual influence during transmission is avoided. Therefore, a large quantity of wiring resources, huge time cost and human resources cost are saved for related projects in the fields like broadcast television, security monitoring and the like.

The invention discloses an implementation method for in-band management of a master-slave time synchronization system. A central webmaster carries out management on slave devices through a master device; the master device sends network management information to the master device; after the master device encodes the network management information, the master device sends the network management information to the slave devices; the slave devices execute corresponding network management operation instructions, and meanwhile, the slave devices return device status information to the master device according to an encoding way. Through improvement of an IRIG-B code, a problem of automatic calculation of a delay of a physical link between the master device and the slave devices is solved, the construction cost is effectively reduced, and meanwhile, the central webmaster carries out network management on all slave devices through the master device, so that the wiring resources are effectively saved.

The present disclosure provides a method for debugging a logic system design, an emulator, and a storage medium. The method includes: cutting the logic system design into at least two blocks, wherein the at least two blocks include a target block; obtaining runtime information of a plurality of stimulus signals of the target block; determining a circuit of the target block structure; and determining the runtime information of the output signals of the plurality of components of the target block based on the runtime information of the plurality of excitation signals of the target block and the circuit structure of the target block.