Method for designing power supply network quickly

Abstract

The invention relates to a algorithm for designing a power supply network quickly. In the algorithm, based on the guarantee for meeting chip power consumption requirement, power supply strips conducting small currents in a uniform power supply network are removed and thus a non-uniform power supply network is formed for optimizing the power supply network after arrangement, and wire laying resources are saved as much as possible while the power supply requirement of a chip is met. Compared with the conventional design scheme, the algorithm for designing the power supply network saves wire laying resources and obviously reduces design iteration time.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit computer aided design, relates to a method for quickly designing a power supply network, and in particular to an algorithm for quickly designing a power supply network. Background technique [0002] In the traditional digital back-end design process, the layout is the first step in the physical design. Only after the size and relative position of each module are determined, the wiring of the power network can start. In order to meet the static power consumption requirements of all modules, it is necessary to conduct some physical analysis when constructing the power network, such as whether the voltage drop on each module is controlled within a certain limit, and its power-ground port P / G pin (Note : P / G pin refers to the power port where each module in the layout is connected to the entire power network) whether it can get enough current from the power network. At the same time, the d...

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Problems solved by technology

Therefore, it is not advisable to rely solely on cyclic iterations to continuously improve the power supply design method. It is necessary to improve the quality of the power supply network design to ensure the power consumption requirements of the chip to reduce the number of iterations.

In addition, in order to control the voltage drop within a certain range, the power network may occupy a large amount of routing resources, resulting in signal routing congestion, which in turn affects the timing closure of the design [3]

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