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428 results about "Error location" patented technology

Techniques for detecting and correcting errors using multiple interleave erasure pointers

Techniques for detecting and correcting burst errors in data bytes formed in a two-level block code structure. A second level decoder uses block level check bytes to detect columns in a two-level block code structure that contain error bytes. The second level decoder generates erasure pointers that identify columns in the two-level block structure effected by burst errors. A first level decoder then uses codeword check bytes to correct all of the bytes in the columns identified by the erasure pointers. The first level decoder is freed to use all of the codeword check bytes only for error byte value calculations. The first level decoder does not need to use any of the codeword check bytes for error location calculations, because the erasure pointers generated by the second level decoder provide all of the necessary error locations. This techniques doubles the error correction capability of the first level decoder.
Owner:HITACHI GLOBAL STORAGE TECH NETHERLANDS BV +1

Radio link protocol (RLP)/point-to-point protocol (PPP) design that passes corrupted data and error location information among layers in a wireless data transmission protocol

InactiveUS7031257B1Reduces or avoids unnecessary packet discardingImprove performanceError preventionTransmission systemsPoint-to-Point ProtocolError location
A radio link protocol (RLP) / point-to-point protocol (PPP) design is disclosed for wireless multimedia packet networks that passes corrupted packet data and error location information among OSI layers. The RLP layer provides erasure data frames and optionally error location indicators to the PPP layer. When the PPP layer has access to the erasure data frames, the data frames can be padded with a predefined value, such as all zeroes “0” to prevent error propagation from one data frame (or octet) to the following data frames (or octets). When the PPP layer has access to the error location information, the PPP layer can detect if the PPP packet header is corrupted. When a valid header is detected, the PPP layer forwards the packet payload to the higher layers (TCP, UDP) whether or not the payload is properly received. Thus, the application has access to all the usable information, so the application can determine whether and how to utilize the information. The RLP / PPP design of the present invention allows packets with partially corrupted payloads to still be forwarded to the UDP layer and then to the application layer.
Owner:ALCATEL-LUCENT USA INC +1

K nearest fuzzy clustering WLAN indoor locating method based on REE-P

The invention provides a K nearest fuzzy clustering WLAN indoor locating method based on REE-P, relating to the indoor locating method in the field of identification. The method comprises the following steps of: 1. measuring and recording a RSS signal received by an user terminal at a point to be located; 2. ensuring K reference points which are most similar to the signal characteristic of the point to be located with a K nearest method; 3. classifying the RSS value of the selected reference points with a fuzzy clustering algorithm, computing the square of the difference between component in each clustering center vector and the RSS value from corresponding AP, accumulating the values in the clustering, and selecting one with the lowest sum; 4. reusing the fuzzy clustering algorithm to classify the positions of all the reference points and select the reference points which have the most same reference points as that selected from step 3; and 5. taking the sum of the reference points from step 3 and step 4, and taking the average coordinate of the reference points to be taken as the position of the point to be located. The method solves the problem of error location caused by the reference points of the K nearest method, and is used for identifying the position.
Owner:HARBIN INST OF TECH

System and Method of Reporting Error Codes in an Electronically Controlled Device

A method of reporting errors in an electronically controlled device, comprises generating a first bit field representative of a severity of an internal error, generating a second bit field representative of a location of the internal error; and generating a third bit field representative of a cause of the internal error. The method also comprises structuring an internal error code, wherein the internal error code includes the first, second, and third bit fields.
Owner:HEWLETT PACKARD DEV CO LP

Low complexity chien search in chase-type decoding of reed-solomon codes

Data is processed by obtaining a length of an error locator polynomial. It is determined whether the length of the error locator polynomial is greater than a threshold. In the event the length of the error locator polynomial is greater than the threshold, performance of a Chien search on the error locator polynomial is skipped. In the event the length of the error locator polynomial is less than or equal to than the threshold, the Chien search is performed on the error locator polynomial to determine one or more roots of the error locator polynomial, where the roots correspond to one or more error locations.
Owner:SK HYNIX MEMORY SOLUTIONS

Error Correction in Multi-Valued (p,k) Codes

InactiveUS20080016432A1Rapidly detect and correct errorCode conversionCyclic codesCommunications systemError location
Methods, apparatus and systems for error correction of n-valued symbols in (p,k) codewords including Reed Solomon codes of p n-valued symbols with n>2 and k information symbols have been disclosed. Coders and decoders using a Linear Feedback Shift Registers (LFSR) are applied. An LFSR can be in Fibonacci or Galois configuration. Errors can be corrected by execution of an n-valued expression in a deterministic way. Error correcting methods using Galois arithmetic are disclosed. Methods using Cramer's rule are also disclosed. Deterministic error correction methods based on known symbols in error are provided, making first determining error magnitudes not necessary. An error location methods using up and down state tracking is provided. Methods and apparatus executing the methods with binary circuits are also disclosed. Systems using the error correcting methods, including communication systems and data storage systems are also provided.
Owner:TERNARYLOGIC

Use of hashing function to distinguish random and repeat errors in a memory system

One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.
Owner:LENOVO GLOBAL TECH INT LTD
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