Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

48results about How to "Inhibition of current increase" patented technology

Plasma processing method, plasma etching method and manufacturing method of solid-state image sensor

A method of plasma processing is offered to suppress generation of interface states, specifically to suppress increase in the dark current of a solid-state image sensor by reducing the interface states. An interlayer insulation film made of silicon nitride film is formed over a silicon substrate by plasma CVD, and a photoresist layer is selectively formed on the interlayer insulation film. Subsequent heating process makes a profile of the photoresist layer round. Next, the interlayer insulation film is plasma-etched using the photoresist layer as a mask and a fluorocarbon gas as an etching gas to form micro lenses. Pulse-time-modulated plasma method in which RF power is supplied intermittently is used to suppress increase in the interface states at silicon-silicon dioxide interface due to an influence of UV light generated in the plasma etching.
Owner:SANYO ELECTRIC CO LTD +1

Semiconductor Device And Manufacturing Method Thereof

A technique of suppressing leak current in a semiconductor device is provided. A semiconductor device, comprises: a semiconductor layer made of a semiconductor; an insulating layer configured to have electric insulation property and formed to cover part of the semiconductor layer; a first electrode layer formed on the semiconductor layer, configured to have a work function of not less than 0.5 eV relative to electron affinity of the semiconductor layer and extended to surface of the insulating layer to form a field plate structure; and a second electrode layer configured to have electrical conductivity and formed to cover at least part of the first electrode layer. A distance between an edge of a part of the first electrode layer that is in contact with the semiconductor layer and the second electrode layer is equal to or greater than 0.2 μm.
Owner:TOYODA GOSEI CO LTD

Solid electrolytic capacitor

A solid electrolytic capacitor includes a capacitor element including a cathode portion and an anode portion, a cathode terminal bonded to the cathode portion, an anode terminal bonded to the anode portion, and an enclosure resin covering the capacitor element. The cathode terminal includes a cathode lower surface portion, a cathode connection portion, and a cathode support portion. The cathode connection portion is connected to an end portion of the cathode lower surface portion on an anode side and bonded to the cathode portion through a conductive adhesive. The cathode support portion is connected to a side portion of the cathode lower surface and brought into contact with a lower surface of the cathode portion on an end portion side of the cathode portion without involving the conductive adhesive therebetween.
Owner:PANASONIC CORP

Semiconductor device and method for manufacturing semiconductor device

During the production of a semiconductor device having a Cu wiring line of a damascene structure, diffusion of fluorine from a CF film that serves as an interlayer insulating film is prevented in cases where a heat treatment is carried out, thereby suppressing increase in the leakage current. A semiconductor device of the present invention having a damascene wiring structure is provided with: an interlayer insulating film (2) that is formed of, for example, a fluorine-added carbon film; and a copper wiring line (4) that is embedded in the interlayer insulating film. A barrier metal layer (6) close to the copper wiring line and a fluorine barrier film (5) close to the interlayer insulating film are formed between the interlayer insulating film and the copper wiring line.
Owner:TOKYO ELECTRON LTD +1

Flip-flop circuit

A flip-flop circuit capable of inhibiting current consumption as well as the circuit scale from increase is provided. This flip-flop circuit comprises a first latch circuit including first and second inverter circuits. A first power supply line capable of switching a supplied potential between a fixing potential supplied for fixing the potentials of output nodes of the first and second inverter circuits and a floating potential supplied for floating the potentials of the output nodes of the first and second inverter circuits is connected to the first latch circuit.
Owner:SEMICON COMPONENTS IND LLC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products