36results about How to "Increased junction" patented technology

The present invention addresses the key challenges in FinFET fabrication, that is, the fabrications of thin, uniform fins and also reducing the source / drain series resistance. More particularly, this application relates to FinFET fabrication techniques utilizing tetrasilane to enable conformal deposition with high doping using phosphate, arsenic and boron as dopants thereby creating thin fins having uniform thickness (uniformity across devices) as well as smooth, vertical sidewalls, while simultaneously reducing the parasitic series resistance.

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source / drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.

A low resistance tunnel junction that uses a natural polarization dipole associated with dissimilar materials to align a conduction band to a valence band is disclosed. Aligning the conduction band to the valence band of the junction encourages tunneling across the junction. The tunneling is encouraged, because the dipole space charge bends the energy bands, and shortens a tunnel junction width charge carriers must traverse to tunnel across the junction. Placing impurities within or near the tunnel junction that may form deep states in the junction may also encourage tunneling in a tunnel junction. These states shorten the distance charge carriers must traverse across the tunnel junction.

A photodiode designed to capture incident photons includes a stack of at least three superposed layers of semiconductor materials having a first conductivity type The stack includes: an interaction layer designed to interact with incident photons so as to generate photocarriers, a collection layer to collect the photocarriers; a confinement layer designed to confine the photocarriers in the collection layer. The collection layer has a band gap less than the band gaps of the interaction layer and confinement layer. The photodiode also includes a region which extends transversely relative to the planes of the layers. The region is in contact with the collection layer and confinement layer and has a conductivity type opposite to the first conductivity type so as to form a p-n junction with the stack.

Method for assembling thermoelectric unicouples is provided and applied with silicon-based nanostructure thermoelectric legs. The method includes preparing and disposing both n-type and p-type thermoelectric material blocks in alternative columns on a first shunt material. The method includes a sequence of cutting processes to resize the thermoelectric material blocks to form multiple cingulated unicouples each having an n-type thermoelectric leg and a p-type thermoelectric leg bonded to a section of the first shunt material. Additionally, the method includes re-disposing these cingulated unicouples in a serial daisy chain configuration with a predetermined pitch distance and bonding a second shunt material on top. The method further includes performing additional cutting processes to form one or more parallel series of thermoelectric unicouples in daisy chain configuration. The first shunt material is coupled to a cold-side heat sink and the second shunt material is coupled to a hot-side heat sink.

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source / drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

A peptide containing 24 amino acid residues that binds to anti-neuronal-glutamate-receptor autoantibodies associated with Rasmussen's encephalitis and that blocks activation of the GluR3 subunit is described. Methods of making the peptide and treating Rasmussen's encephalitis are also disclosed. Autoantibodies to other glutamate receptor subunits are associated with paraneoplastic neurodegenerative disease, amyotrophic lateral sclerosis, and neurodegenerative disease of unknown diagnosis. Methods of screening patients and of monitoring patients being treated for these disorders and syndromes are further described.

An object of this invention is to provide a Schottky diode structure to increase the contact area at a Schottky junction between the Schottky Barrier metal and a semiconductor substrate. The larger contact area of the Schottky junction is, the lower of the forward voltage drop across the Schottky diode will be, thereby improving the performance and efficiency of the Schottky diode.The present invention also discloses that a plurality of trenches with adjacent top mesas can be used to form a Schottky diode with even larger contact area, wherein the trenches are built using the isolation area between two cells of MOSFET with minimum extra overhead by shrinking the dimension of pitch between two trenches.

Off-chip driver (OCD) NMOS transistors with ESD protection are formed by interposing an P-ESD implant between the N+ drain regions of OCD NMOS transistors and the N-well such that the P-ESD surrounds a section of the N-well. The P-ESD implant is dosed less than the N+ source / drain implants but higher than the N-well dose. In another embodiment, N-well doping is used along with P-ESD doping, where the P-ESD doping is chosen such that it counterdopes the N-well underneath the N+ drains. The N-well, however, still maintains electrical connection to the N+ drains. This procedure creates a larger surface under the area where the junction breakdown occurs and an increased radius of curvature of the junction. The P-ESD implant is covered by N-type on three sides creating better parasitic bipolar transistor characteristics.

The present invention provides a liquid container which has a check valve for preventing a flow of outside air into its inside and which is capable of maintaining the performance of the check valve constant. An ink pack (25) includes a bag portion (36), which holds an outlet portion by heat-welding. An internal space (S) is formed in the bag portion (36), and ink is contained therein. The outlet portion has a first flow path forming component (41). A first recess portion (47) is recessed from the one side surface (41a) of the first flow path forming component (41). First and second ink flow paths (46, 51), which communicate with the internal space (S), extend from a bottom surface (47a) of this first recess portion (47). A valve seat (53) is formed in a projecting shape so as to surround the second ink flow path (51). A laminate film (36a) sealingly closes the first recess portion (47). Thus, a valve body accommodating chamber (55) is formed. The valve body accommodating chamber (55) accommodates a first valve body (58). The valve body (58) and the valve seat (53) form a first valve device (59).

A semiconductor light-emitting element including a substrate, a laminated semiconductor layer including a light-emitting layer formed over the substrate, one electrode (111) formed over the upper face of the laminated semiconductor layer, and an other electrode formed over the exposed surface of the semiconductor layer, from which the laminated semiconductor layer is partially cut off. The one electrode (111) includes a junction layer (110) and a bonding pad electrode (120) formed to cover the junction layer. The bonding pad electrode has a maximum thickness larger than that of the junction layer, and is composed of one or two or more layers. Slopes (110c), (117c) and (119c), which are made gradually thinner toward the outer circumference, are formed in the outer circumference portions (110d) and (120d) of the junction layer and the bonding pad electrode. Also disclosed is a method for manufacturing the element and a lamp.

The present invention pertains to a method of manufacturing a bi-metal screw comprising a sequence of procedures; wherein, the process preparation is for arranging a shank portion and a drilling portion made of different materials; the shank portion has a planar welding surface defined thereon; in particular, the drilling portion includes a conical section with a conical surface defined on the top face thereof. While operating, the conical section is gradually welded to the planar welding surface to form a composite screw, so as to smooth the air away for preventing the interspaces generated within the junction of the two portions and rendering the composite screw not to be slanted aside. Subsequently, an integral bi-metal screw is formed through the processes of precisely cutting and formation, thereby increasing the quality of the screw.

A system for determining the position of a mover as the mover transitions between segments along a track includes a first controller on a first track segment and a second controller on a second track segment. The first and second track segments are adjacent to each other and a junction is located between the two segments. The first and second controllers are in communication with each other and share a locally determined position value with the other controller. Each controller determines a compensated position value as a function of both a locally determined position value and the shared position value received from the other controller. Each controller utilizes the compensated value of the position value as determined on that controller to control operation of the mover while it is present on the corresponding track segment.

A semiconductor device includes a normally-on junction FET having a gate electrode, a source electrode and a drain electrode and a normally-off MOSFET having a gate electrode, a source electrode and a drain electrode. The source electrode of the junction FET is electrically connected to the drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series. The gate electrode of the junction FET is electrically connected to the gate electrode of the MOSFET.

A system for determining the position of a mover as the mover transitions between segments along a track includes a first controller on a first track segment and a second controller on a second track segment. The first and second track segments are adjacent to each other and a junction is located between the two segments. The first and second controllers are in communication with each other and share a locally determined position value with the other controller. Each controller determines a compensated position value as a function of both a locally determined position value and the shared position value received from the other controller. Each controller utilizes the compensated value of the position value as determined on that controller to control operation of the mover while it is present on the corresponding track segment.

The present invention provides a liquid container which has a check valve for preventing a flow of outside air into its inside and which is capable of maintaining the performance of the check valve constant. An ink pack (25) includes a bag portion (36), which holds an outlet portion by heat-welding. An internal space (S) is formed in the bag portion (36), and ink is contained therein. The outlet portion has a first flow path forming component (41). A first recess portion (47) is recessed from the one side surface (41a) of the first flow path forming component (41). First and second ink flow paths (46, 51), which communicate with the internal space (S), extend from a bottom surface (47a) of this first recess portion (47). A valve seat (53) is formed in a projecting shape so as to surround the second ink flow path (51). A laminate film (36a) sealingly closes the first recess portion (47). Thus, a valve body accommodating chamber (55) is formed. The valve body accommodating chamber (55) accommodates a first valve body (58). The valve body (58) and the valve seat (53) form a first valve device (59).

A thin film transistor array panel is provided according to one or more embodiments. In an embodiment, the thin film transistor array panel includes: a base substrate that has a display area and a peripheral area; a plurality of thin film transistors that are formed in the display area; a plurality of signal input pads that are formed in the peripheral area and that are formed long in a first direction; and a plurality of signal lines that are connected to the thin film transistors and the signal input pads, wherein at least a part of each of the plurality of signal input pads is arranged in a line along the first direction.

A thin film transistor array panel is provided according to one or more embodiments. In an embodiment, the thin film transistor array panel includes: a base substrate that has a display area and a peripheral area; a plurality of thin film transistors that are formed in the display area; a plurality of signal input pads that are formed in the peripheral area and that are formed long in a first direction; and a plurality of signal lines that are connected to the thin film transistors and the signal input pads, wherein at least a part of each of the plurality of signal input pads is arranged in a line along the first direction.

A use of a stem cell conditioned medium to induce ZO-1 proteins expression for skin regeneration, repair and finning is revealed herein. First, mesenchymal stem cells are cultured in a cell culture dish containing complete growth media, wherein the complete growth media include α-MEM, fetal bovine serum, and human-basic fibroblast growth factors. After mesenchymal stem cells are sub-cultured in the complete growth media for three times, a conditioned medium which can effectively increase the activation of tight junction protein Zonula occludens-1 (ZO-1) can be acquired from the basal medium.

Diodes for use in FinFET technologies having increased junction electric fields without the need for increased dopant concentrations, as well as methods, apparatus, and systems for fabricating such diodes. The diodes may comprise a semiconductor substrate and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises an N channel doped region comprising an N channel dopant, and the semiconductor substrate further comprises a plurality of P channel doped regions comprising a P channel dopant, wherein each of the P channel doped regions is disposed under one of the plurality of fins and is adjacent to the N channel doped region of the fin.

A use of a stem cell conditioned medium to induce ZO-1 proteins expression for skin regeneration, repair and finning is revealed herein. First, mesenchymal stem cells are cultured in a cell culture dish containing complete growth media, wherein the complete growth media include α-MEM, fetal bovine serum, and human-basic fibroblast growth factors. After mesenchymal stem cells are sub-cultured in the complete growth media for three times, a conditioned medium which can effectively increase the activation of tight junction protein Zonula occludens-1 (ZO-1) can be acquired from the basal medium.

Provided are dietary supplement composition comprising one or both of L-theanine and a trace mineral complex, optionally in combination with bioactive peptides, in an amount or amounts individually or in combination effective to promote gut health. Further optional components include a fiber oligosaccharide prebiotic, a polyphenol prebiotic, and a polynucleotide or blend. Examples of benefits include one or more of: —an increase in the amount of total short-chain fatty acid production or of at least one of propionate, acetate and butyrate; —an increase the expression or level of at least one tight junction protein (for example, claudin-1, claudin-3, claudin-4, occludin, or a zona occludens protein) or mucin-3 or decrease the expression or level of claudin-2; —an increase in transepithelial electrical resistance; —an increase in the abundance or diversity of a member or phylum of the intestinal bacterial community of the Intestinal lumen or mucus area (for example, Firmicutes, Bacteroidetes, Lactobacilli, Bifidobacteria, F. prausnitzii, or A. muciniphila); —an increase in the expression or level of at least one intestinal surface area marker protein (for example, villin, myosin, cadherin or sucrase-isomaltase). Methods for using such supplements are also disclosed.