55results about "Reliability increase in bipolar transistors" patented technology

An apparatus and method for driving an output signal in a high speed integrated circuit. The apparatus and methods enable the output voltage swing from the driver to exceed the breakdown voltage of any individual element in the output driver. A high speed driver can utilize one or more transistors in a stacked configuration, such that the breakdown voltage of the entire stacked configuration is based on the number of transistors in the stack. The driver is configured to distribute the output voltage substantially equally among each of the stacked transistors, such that the driver is able to source an output voltage swing that is greater than the breakdown voltage of any individual transistor in the driver.

The invention discloses a variable coding method for implementing chip reuse. The method includes the following steps: using at least two same integrated circuit chips of which each controls logic truth tables based on the differences of gating signals; introducing at least one logical control signal as a gating signal; controlling the logic control signal, such that respective integrated circuit chip controls the logic truth table accordingly. The invention also discloses a communication terminal for implementing chip reuse by using the variable coding method. According to the invention, two completely identical integrated circuit chips or more are enabled to implement different logic control, so that chip types that implement system functions are reduced, development cost of an integrated circuit system is greatly reduced as well as supply chains for mass production.

An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs) (202), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of power switch pairs (204), each power switch pair coupled to an emitter of a respective one of the plurality of BJTs; a plurality of sensing switch pairs (206), each sensing switch pair being respectively coupled to a plurality of BJTs The emitter of each of the BJTs, the first switch of each sense switch pair is coupled to the first node (Vbel), and the second switch of each sense switch pair is coupled to the second node (Vbe2); a first current source (208) coupled to the first switch in each power switch pair; and a second current source (210) coupled to the second switch in each power switch pair .

An n-type transistor and a p-type transistor are connected in series such that, when the two transistors are turned on, current flows from the collector of the n-type transistor to the collector of the p-type transistor. A positive-feedback capacitor is connected between the collector of one transistor and the base of the other transistor. The two transistors turn on together when the base voltage of the n-type transistor exceeds the base voltage of the p-type transistor by at least the sum of the turn-on threshold voltages of the two transistors and (i) the two transistors turn off together when the base voltage of the n-type transistor fails to exceed the base voltage of the p-type transistor by at least that sum. The positive-feedback capacitor ensures that the two transistors turn fully on and off together. In certain embodiments, the circuitry can be controlled to operate as a current pulse generator.

The application discloses an input buffer circuit and a memory. The input buffer circuit of this application, by configuring the input high voltage threshold to be different from the input low voltage threshold, when the input signal is between the input high voltage threshold and the input low voltage threshold, the logic output signal does not perform state switching, thereby eliminating noise on the input signal interference. That is, the present application can filter out the noise in the input signal, avoid the abnormal state of the logic output signal corresponding to the input signal, and ensure the normal operation of the device.

The invention discloses a self-locking circuit and a matching fast unlocking circuit after self-locking, including a self-locking circuit and a fast unlocking circuit, the self-locking circuit is connected with the fast unlocking circuit, and the Vcc pin of the self-locking circuit The fifth resistor is connected to the negative electrode of the second zener diode, the anode of the second zener diode is connected to the emitter of the second switching transistor, and the second capacitor and the second capacitor are connected in parallel between the base and the emitter of the second switching transistor. Six resistors, the collector of the third switching transistor is connected to the base of the second switching transistor, the third capacitor and the seventh resistor are connected in parallel between the emitter and the base of the third switching transistor, and the base of the third switching transistor is also It is connected to the PROTECT pin, and the emitter of the third switching transistor is also connected to the GND pin; the invention not only retains the self-locking characteristic of the self-locking circuit, but also solves the problem caused by the long unlocking time of the self-locking circuit after the input power is cut off.

A method for reducing narrow gate width effects in an integrated circuit includes finding the smallest transistor channel widths that are larger than the minimum width for the technology for library cells that produce logic blocks that meet timing constraints while using the least amount of power and have the smallest possible area. The method may include characterizing a device library while varying process, voltage and temperature parameters, and synthesizing an HDL representation of a functional logic block including cells from the device library. The method may also include determining whether timing, area, and power values of the functional logic block are within a predetermined range. In response to the timing, area, and power values not being within the predetermined range, iteratively increasing the channel width of at least a portion of the transistors of at least one of the cells in the device library.

The invention discloses an on-off input circuit for a relay protection testing device. The circuit consists of a voltage stabilizing diode, a rectification bridge circuit, a photoelectric coupler circuit, a triode switching circuit, a filter capacitor and a voltage stabilizing reference power circuit. The on-off input circuit for the relay protection testing device is self-adaptive about various types of the input patterns, and the pre-configuration does not need to be executed; and the on-off input circuit for the relay protection testing device is self-adaptive about the polarity of the active input, even the reverse connection can be correctly identified, and the potential safety hazard cannot be caused by the polarity of the input. The on-off input circuit for the relay protection testing device is provided with the potential output, and is capable of providing the power for the high-speed output of the Darlington tube type, and reducing the external connections.