Nuclear hardening D-latch

A latch and latching technology, applied in electrical components, reliability improvement and modification, logic circuits, etc., can solve the problems of multi-hardware, dual-node fault tolerance, and high power consumption of anti-irradiation D latches

Pending Publication Date: 2019-03-29
ZHONGBEI UNIV +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The present invention aims to solve the problems that the existing anti-radiation D latch needs more hardware, high power consumptio

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  • Nuclear hardening D-latch
  • Nuclear hardening D-latch

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Embodiment Construction

[0068] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0069] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0070] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0071] see figure 1 Describe this embodiment, the anti-nuclear hardened D latch in this embodiment include...

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Abstract

The invention discloses a nuclear hardening D-latch, and belongs to the field of anti-nuclear reinforcement in integrated circuit reliability. The problem that according to existing anti-radiation D-latches, more hardware is needed, power consumption is high, delay time is long, and fault tolerance for flipped double nodes cannot be realized is solved. The latch of the invention includes two inverters I1 and I2, 28 NMOS transistors N1 to N28, and 12 PMOS transistors P1 to P12. Used devices are few, volume is small, a structure is simple, and due to that the used devices are few, power consumption of the entire latch is reduced, and hardware overheads are lower. A signal at an input end of the latch can be transmitted to an output port simply through one transmission gate, data transmissiontime is short, fault tolerance for any-single-node and double-node flipping can also be realized, and thus fault tolerance protection against single-node and double-node flipping is realized. The latch of the invention can provide protection for application of integrated circuit chips in high-radiation environments (such as aerospace and terrestrial nuclear power plants).

Description

technical field [0001] The invention belongs to the field of anti-nuclear hardening in integrated circuit reliability. Background technique [0002] The digital D latch plays a very important role in sequential digital circuits, and the information latched by it can be used by the next-level circuit. However, if the node storing information is changed by the interference of external radiation particles, it will affect the function of the subsequent circuit, resulting in an error in the entire circuit system. [0003] The existing anti-irradiation D latches can resist the interference of external radiation particles, but they simply copy multiple units and use three-mode redundancy or even four-mode redundancy for reinforcement. Although it can achieve anti-radiation Double-node flipping, but the ability to resist double-node flipping is poor, and even the flipped dual-node cannot be fault-tolerant. On the other hand, the existing anti-irradiation D latch requires more hardw...

Claims

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Application Information

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IPC IPC(8): H03K19/003H03K19/00
CPCH03K19/001H03K19/00307
Inventor 郭靖朱磊
Owner ZHONGBEI UNIV
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