Anti-double-node-upset D latch

Abstract

The invention provides an anti-double-node-upset D latch and belongs to the field of nuclear hardening in integrated circuit reliability. The problems that according to an existing latch, required hardware is much, an area is large, power consumption is high, propagation delay time is long, anti-double-node-upset capability is poor, and fault tolerance to double-node-upset cannot be realized are solved. The D latch comprises 20 NMOS transistors N1 to N20 and 12 PMOS transistors P1-P12. Employed devices are few. A size is small. A structure is simple. The employed devices are few, so power consumption of the whole latch is reduced, and relatively low hardware cost is realized. A signal at an input end of the latch can be transmitted to an output port through a transmission gate. Data transmission time is short. The fault tolerance to any single-node and double-node-upset can be realized, so anti-single-node and anti-double-node-upset fault tolerance protection is realized. The D latch is particularly applicable to aerospace, space flight and a nuclear power plant with nuclear radiation effect.

Description

technical field [0001] The invention belongs to the field of anti-nuclear hardening in integrated circuit reliability. Background technique [0002] D latches are widely used in various digital integrated circuits, such as decoders and timing control circuits. However, since the latch has the function of storing information, radiation particles will change the information it holds, thus causing errors in the electronic system. [0003] Existing latches generally use three-mode redundancy or even more mode redundancy to achieve resistance to interference from external radiation particles. However, it requires a lot of hardware (up to 102 transistors), large area, and high power consumption. , Propagation delay time is long, and although anti-double-node flipping can be realized, the ability to resist double-node flipping is poor, and even the fault tolerance to double-node flipping cannot be realized. Therefore, the above problems need to be solved urgently. Contents of th...

AI Technical Summary

Problems solved by technology

[0004] The present invention aims to solve the problems that existing latches require more hardware, large area, high power consumption, long propagation delay time, poor ability to resist double-node flipping, and failure to realize fault tolerance to double-node flipping. Provides a new type of double-node flip-resistant D-latch

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