236results about "Logic circuits using semiconductor devices" patented technology

A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

A microcontroller with analog / digital Programmable System On-a-Chip (PSoC) architecture including multiple digital PSoC blocks and multiple analog PSoC blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and / or separate applications. The PSoC architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The PSoC array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the PSoC blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input / output data between all analog and digital blocks.

The present disclosure provides a method of operation of a quantum processing element and an advanced processing apparatus comprising a plurality of quantum processing elements operated in accordance with the method. Embodiments of the methods disclosed allow using the quantum properties of an MOS structure and a donor atom embedded in the semiconductor to implement electron and nuclear spin qubits and provide multi-qubit coupling, including coupling at longer distances facilitated by a resonator.

In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

A function reconfigurable semiconductor device is provided. The function reconfigurable semiconductor device includes a plurality of function cells, each of the function cells being a basic unit which realizes a function; each of the function cells including a plurality of threshold elements; each of the threshold elements including means which stores a threshold value; and wherein a function which is realized by the function cell is determined by determining the threshold value in each of the threshold elements. In addition, the semiconductor device includes a nonvolatile memory which stores data for realizing the function in the function cells.

Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.

A logic circuit performs a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area. Adjacent ones of the logic circuits have a common source diffusion layer so that the load capacitance with respect to the inverse signal can be significantly reduced, thus enabling the high speed operation.

The present invention relates to a SET / RESET latch circuit a Schmitt trigger circuit, and a MOBILE based D-type flip flop circuit and frequency divider circuit using the SET / RESET latch circuit and Schmitt trigger circuit. The SET / RESET latch circuit is configured with CML-type transistors and negative differential resistance diodes. The SET / RESET latch circuit can be applied to very high speed digital circuits.

The present invention provides a single wire programmable Micro Electromechanical System (MEMS) microphone and a programming method and system thereof. The single wire programmable MEMS microphone includes an MEMS sensor and an Application Specific Integrated Circuit (ASIC) chip connected to each other; the MEMS sensor is used for implementing acoustic-electric conversion; the ASIC chip includes an OUT interface, so that an upper computer judges, according to an output signal of the OUT interface, whether the ASIC chip is in a normal start mode or a programming mode, where if the output signal of the OUT interface is at a high level, the ASIC chip is in the normal start mode, and otherwise, the ASIC chip enters the programming mode. Through the present invention, multiplexing of the OUT interface of the MEMS microphone is implemented, and gain configuration for the OTP memory in the ASIC chip is implemented by multiplexing the OUT interface, thereby achieving calibration of the gain of the MEMS microphone product after package.

A transceiver suitable for interfacing a logic device to a shared bus includes a transmit node that receives an input signal from the logic device and an I / O node, that is coupled to the shared bus. The transceiver may be designed for use with a shared-bus, single master, multiple slave architecture, e.g., a Local Interconnect Network (LIN). In a LIN compliant implementation, the transceiver may be suitable for use in at least some types of automobiles and other motorized vehicles. Control logic coupled to the transmit node may assert a current driver enable signal in response to detecting an assertion of the input signal. A current driver of the transceiver is configured to draw a time varying driver current from the shared bus node after detecting an assertion of the current driver enable signal. The driver current may cause a sinusoidal transition of the shared bus voltage.