77 results about "Spin transistor" patented technology

Each layer in the magnetic multilayer film is a closed ring or oval ring and the magnetic moment or flux of the ferromagnetic film in the magnetic unit is in close state either clockwise or counterclockwise. A metal core is put in the geometry center position in the close-shaped magnetic multilayer film. The cross section of the metal core is a corresponding circular or oval. A MRAM is made of the closed magnetic multilayer film with or without a metal core. The close-shaped magnetic multilayer film is formed by micro process method. The close-shaped magnetic multilayer film can be used broadly in a great variety of device that uses a magnetic multilayer film as the core, such as MRAM, magnetic bead in computer, magnetic sensitive sensor, magnetic logic device and spin transistor.

A spin transistor includes a first conductive layer that is made of a ferromagnetic material magnetized in a first direction, and functions as one of a source and a drain; a second conductive layer that is made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction, and functions as the other one of the source and the drain. The spin transistor also includes a channel region that is located between the first conductive layer and the second conductive layer, and introduces electron spin between the first conductive layer and the second conductive layer; a gate electrode that is located above the channel region; and a tunnel barrier film that is located between the channel region and at least one of the first conductive layer and the second conductive layer.

The invention relates to a magnetic tunnel junction of a spinel oxide potential barrier, and the application in device thereof. The potential barrier of the magnetic tunnel junction is made of spinel oxides. The tunnel junction may be of a single potential barrier structure or of a double potential barrier structure. The novel single potential barrier magnetic tunnel junction provided by the invention can be applied to a spintronic device and comprises a magneto-dependent sensor, a magnetic random access memory unit, a magnetic logic device unit, a spin transistor and a spin field effect transistor. According to the magnetic tunnel junction based on novel potential barriers, the mismatch degree between a potential barrier layer and a magnetic crystal lattice is quite small, while a high room temperature tunneling magneto-resistor ratio is maintained, the bias dependence feature is quite weak, and the breakdown voltage is improved.

A spin transistor having wide ON/OFF operation margin and producing less noise is provided. The spin transistor includes a substrate having a channel, a source, a drain and a gate formed on the substrate. The source and the drain are formed to have magnetization directions perpendicular to the length direction of the channel. The ON/OFF operations of the spin transistor can be controlled by generating a spin-orbit coupling induced magnetic field to have a direction parallel or anti-parallel to the magnetization directions of the source and the drain.

The invention relates to a magneto-electric spin-FET including a gate film of chromia and a thin film of a conductive channel material which may be graphene, InP, GaAs, GaSb, PbS, MoS₂, WS₂, MoSe₂, WSe₂ and mixtures thereof. The chromia, or other magneto-electric, and conduction channel material are in intimate contact along an interface there between. The resulting magneto-electric device may be voltage-controlled and provide non-volatile memory.

Certain embodiments provide a spin memory including a memory cell including a ferromagnetic stacked film that has a stacked structure in which a first ferromagnetic layer, a first nonmagnetic layer, a second ferromagnetic layer, a second nonmagnetic layer, and a third ferromagnetic layer are stacked in this order or reverse order, the third ferromagnetic layer and the second ferromagnetic layer being antiferromagnetically exchange-coupled via the second nonmagnetic layer. The ferromagnetic stacked film includes a current path in which a first and second write currents flow from the first ferromagnetic layer to the third ferromagnetic layer to write a first and second magnetization states into the first ferromagnetic layer respectively, and the second write current is higher than the first write current.

The spin transistor in accordance with the present invention comprises a magnetoresistive element having a fixed layer, a free layer, and a semiconductor layer provided between the fixed layer and free layer; a source electrode layer electrically connected to one end face in a laminating direction of the magnetoresistive element; a drain electrode layer electrically connected to the other end face in the laminating direction of the magnetoresistive element; and a gate electrode layer laterally adjacent to the semiconductor layer through a gate insulating layer provided on a side face of the semiconductor layer.

A spin transistor useful for device miniaturization and high-density integration is provided. The spin transistor includes: a semiconductor substrate including a channel layer; ferromagnetic source and drain disposed on the semiconductor substrate to be separated from each other and to be magnetized in a direction perpendicular to a surface of the channel layer; a gate formed on the semiconductor substrate between the source and the drain to adjust spins of electrons passing through the channel layer, wherein spin-polarized electrons are injected from the source to the channel layer, and the electrons injected into the channel layer pass though the channel layer and are injected into the drain, and wherein the spins of the electrons passing through the channel layer undergo precession due to a spin-orbit coupling induced magnetic field according to a voltage of the gate.

A spin transistor includes a first ferromagnetic layer, a second ferromagnetic layer, a semiconductor layer between the first and second ferromagnetic layers, and a gate electrode on or above a surface of the semiconductor layer, the surface being between the first and second ferromagnetic layers. The first ferromagnetic layer comprises a ferromagnet which has a first minority spin band located at a high energy side and a second minority spin band located at a low energy side, and has a Fermi level in an area of the high energy side higher than a middle of a gap between the first and second minority spin bands.

A spin transistor conducive to the miniaturization and large scale integration of devices, because a magnetization direction of a source and a drain is determined by a direction of the epitaxial growth of a ferromagnet. The spin transistor includes a semiconductor substrate having a channel layer formed thereinside; ferromagnetic source and drain epitaxially grown on the semiconductor substrate and magnetized in a longitudinal direction of the channel layer due to magnetocrystalline anisotropy—the source and drain being disposed spaced apart from each other in a channel direction and magnetized in the same direction—; and a gate disposed between the source and the drain to be insulated with the semiconductor substrate and formed on the semiconductor substrate to control the spin of electrons that are passed through the channel layer.

Spin transistors and related memory, memory systems, and methods are disclosed. A spin transistor is provided by at least two magnetic tunnel junctions (MTJs) with a shared multiferroic layer. The multiferroic layer is formed from a piezoelectric (PE) thin film over a ferromagnetic thin film (FM channel) with a metal electrode (metal). The ferromagnetic layer functions as the spin channel and the piezoelectric layer is used for transferring piezoelectric stress to control the spin state of the channel. The MTJ on one side of the shared layer forms a source and the MTJ on the other side is a drain for the spin transistor.

This invention is about a three-terminal spin transistor magnetic random access memory and the method to make it with a narrow foot print. The first terminal, a bit line, is connected to the top magnetic reference layer, and the second terminal is located at the middle memory layer which is connected to the underneath CMOS control circuit through VIA and the third one, a digital line, is a voltage gate with a narrow point underneath the memory layer across an insulating layer which is used to reduce the write current when it is turned on. The fabrication includes formation of a large VIA base, formation of digital line, formation of memory cell & VIA connection and formation of the top bit line. Dual photolithography patterning and hard mask etch are used to form the digital line pillar and small memory pillar. Oxygen plasma ion implantation is used to define an insulating region underneath the memory cell and metallic ion implantation is used to convert a buried dielectric VIA base outside the center memory pillar into an electric conductive path between middle memory cell and underneath CMOS device.

The invention provides a magnetic multilayer film unit, comprising a magnetic multilayer film core unit and a magnetic moment control unit, wherein the magnetic multilayer film core unit comprises a free layer; the magnetic moment control unit comprises two conducting layers; and the free layer of the magnetic multilayer film core unit is positioned in an electric field formed by the two conducting layers. In addition, the invention also provides a corresponding preparation method and a magnetic moment overturning control method of the magnetic multilayer film unit. In the invention, the power consumption of the devices is greatly reduced, and the integration level of the devices can be improved; a preparation process and a semiconductor process are compatible so as to be beneficial to large-scale industrial production; and the magnetic multilayer film unit is beneficial to miniaturization of spintronic devices and has the advantage of radiation resistance. The magnetic multilayer film unit can be widely applied in the spintronic devices such as logic devices, nonvolatile storages, spinning transistors and various sensors and the like in the field of the future computer information communication industry. The invention is beneficial to widening of the application range of the spintronic devices.

The invention discloses a single-electron magnetic resistance structure and application thereof, such as a spin diode, a spin transistor, a sensor, a magnetic random access memory and a magnetic logic device unit. A GMR (Giant Magnetic Resistance) quantum dot single-electron tunneling magnetic resistance structure comprises a substrate as well as a bottom conducting layer, a first barrier layer, a GMR magnetic quantum dot layer, a second barrier layer and a top conducting layer which are arranged on the substrate. A double-barrier magnetic quantum dot structure comprises a core film layer comprising a bottom electrode, a first barrier layer, a magnetic quantum dot layer, a second barrier layer and a top electrode from bottom to top. Due to the combination with a coulomb blockade effect and a tunneling magnetic resistance effect, the invention controls coulomb energy level resonant tunneling passing through quantum dots by utilizing an external magnetic field to improve tunneling magnetic resistance. The invention can effectively improve the tunneling magnetic resistance effect by utilizing a magnetic resistance design formed by coulomb blockade and improve the signal to noise ratio of device application, and simultaneously reduces tunneling current by utilizing single-electron tunneling, thereby reducing the power consumption of device application.