130 results about "Controller architecture" patented technology

Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.

A fault tolerant, multi-protocol shelf management controller architecture that is extensible provides an intelligent platform management interface that is version indifferent as well as programmable and reconfigurable. The shelf management controller is arranged in a dual redundant configuration in a client-server mode and has a message driven configuration with the messages conforming to the Intelligent Platform Management Interface (IPMI) specification as extended by PICMG 3.0. In one embodiment, each shelf management controller includes at least one bit stream processor comprising sequenced stage machines implementing one or more finite state machines associated with one or more devices that are under control of the shelf management controller. The finite state machines could be hardware or software based. The shelf management controller is also modeled as a layered architecture that includes an IPMI API layer. The IPMI API layer enables the shelf manager to interface with legacy and future IPMI specifications.

An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and / or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

A GPS receiver includes an RF front end for acquiring and tracking a satellite signal and a baseband processor configured to preserve power. The baseband processor includes a GPS engine configured to process the satellite signal and generate a PVT fix, a power supervisory module for receiving the PVT fix, and a user state module that determines an environmental state, wherein the power supervisory module may power down the GPS receiver for a period of time based on a result of the determined environment state. The baseband processor also includes a time-based management module that adjusts the TCXO in response to the determined environmental state. The GPS receiver includes a plurality of operation modes, each of which is associated with a plurality of tracking profiles.

A microcontroller with analog / digital Programmable System On-a-Chip (PSoC) architecture including multiple digital PSoC blocks and multiple analog PSoC blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and / or separate applications. The PSoC architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The PSoC array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the PSoC blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input / output data between all analog and digital blocks.

Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for storing microcode instructions; execution circuitry operable to execute microcode instructions from the control store; and means for loading a suite of one or more microcode-device modules defining an optional peripheral device, the optional peripheral device being implemented by microcode instructions executed by the execution circuitry in accordance with the definition provided by the microcode-device modules.

An embedded electronic system built-in self-test controller architecture that facilitates testing and debugging of electronic circuits and in-system configuration of programmable devices. The system BIST controller architecture includes an embedded system BIST controller, an embedded memory circuit, an embedded IEEE 1149.1 bus, and an external controller connector. The system BIST controller is coupled to the memory circuit and the IEEE 1149.1 bus, and coupleable to an external test controller via the external controller connector. The external test controller can communicate over the IEEE 1149.1 bus to program the memory and / or the system BIST controller circuitry, thereby enabling scan vectors to be debugged by the external test controller and then downloaded into the memory for subsequent application to a unit under test by the system BIST controller.

A mechanism for facilitating configuration of port-type Peripheral Component Interconnect Express / Serial Advanced Technology Attachment host controller architecture is described. In one embodiment, an apparatus includes a plurality of PHYs to be used as Peripheral Component Interconnect Express (PCIe) ports and Serial Advanced Technology Attachment (SATA) ports, and logic to facilitate swapping of one or more of the plurality of PHYs between being the PCIe ports and the SATA ports.

The invention discloses an SDN-based space-space-ground controller deployment architecture and a control method, the controller architecture comprises three network segments of a space-based network,a space-based network and a foundation network, and the space-based network realizes controller dynamic deployment on an unmanned aerial vehicle; introducing an upper SDN controller to the top of eachnetwork segment controller; wherein the SDN network architecture of the upper SDN controller comprises an infrastructure layer, a network control layer and an application layer from bottom to top; the network control layer is used for collecting and maintaining a global topological structure, a link state and flow state information, issuing a control message, introducing an SDN architecture, decoupling a data plane and a control plane, providing a unified programming interface, and configuring and managing nodes in a network in a unified manner. According to the invention, multiple optimization objectives of minimizing the propagation time delay between the switch and the controller and improving the load balance degree of the controller are realized.

The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is disclosed for loading unaligned data stored in several memory locations, including a step of loading a first part of the unaligned data into a first storage location and rotating the first part from a first position to a second position in the first memory location. Next a second part of the unaligned data is loaded into a second storage location and rotated from one position to another position. Then the first storage location is combined with the second storage location using a logical operation into a result storage location. The storage locations may be, for example, 64-bit registers. The logical operation may be a bit-wise OR operation. The method may optionally include, performing masking, zero-extending and / or sign extending operations on the first storage location, when the first part of the unaligned data is in the second position of the first storage location.