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55results about How to "Reduce Mismatch Problems" patented technology

Light-emitting diode with composite polar face electron blocking layer

The invention discloses a light-emitting diode with a composite polar face electron blocking layer. The light-emitting diode comprises a substrate (101), a metal polar face n-type nitride layer (102), a metal polar face multiple quantum well layer (103), a metal polar face p-type nitride layer (104), a composite polar face p-type electron blocking layer (105) composed of a metal polar face p-type electron blocking layer (1051) and a nitrogen polar face p-type electron blocking layer (1052), a nitrogen polar face p-type nitride layer (106), an n electrode (7) arranged on the metal polar face n-type nitride layer and a p electrode (8) arranged on the nitrogen polar face p-type nitride layer, and the layers and the electrodes are arranged sequentially from bottom to top. A high electronic barrier is formed on a conduction band by the composite polar face electron blocking layer and blocks electrons from crossing a multiple quantum well active region to enter a p-type region, leakage currents can be reduced, and the probability of radiative recombination of the electrons and holes is improved.
Owner:SOUTHEAST UNIV

Light emitting diode epitaxial wafer and fabrication method thereof

The invention discloses a light emitting diode epitaxial wafer and a fabrication method thereof, and belongs to the technical field of semiconductors. The fabrication method comprises the steps of providing a patterned sapphire substrate (PSS); forming an aluminum nitride buffer layer on a surface, on which patterns are arranged, of the PPS, wherein the aluminum nitride buffer layer comprises first parts and second parts, the first parts are arranged on the patterns, the second parts are arranged among the patterns; coating photoresist on the aluminum nitride buffer layer, wherein the thickness of the photoresist arranged on the first parts is smaller than the thickness of the photoresist arranged on the second parts; performing dry etching on the photoresist until the photoresist arranged at the tops of the first parts is removed; removing the tops of the first parts; laying a silicon dioxide material; removing the residual photoresist to form a silicon dioxide layered structure; and sequentially growing an N-type gallium nitride layer, a light emitting layer and a P-type gallium nitride layer. By the fabrication method, the epitaxial defect of a top end of the PPS caused by the aluminum nitride buffer layer can be prevented, and lattice mismatching also can be buffered by the aluminum nitride buffer layer.
Owner:HC SEMITEK ZHEJIANG CO LTD

Digital correction method for array analog to digital converter of high-performance CMOS image sensor

The invention belongs to the field of semiconductor image sensing, and specifically relates to a digital correction method for an array analog to digital converter of a high-performance CMOS image sensor. The invention provides an algorithm based on a multi-way collaborative digital correction technology. In particular, for the features that the number of the ADCs in the array ADC of the CIS is high, the area of a single ADC is very small and capacitance mismatch is high, according to the algorithm, an analog to digital converter array which is applied to the CIS and is realized by matching with the algorithm fully is designed. A low working voltage of 1.8V is employed in the integral design. The pixel voltage of the image sensor passes through a variable gain amplifier (VGA), then is directly sent to the analog to the digital converter (ADC) array for conversion, and then is sent to a digital correction engine for calculation. The array analog to digital converter applied to the CMOS image sensor is taken as an integral system. The mismatch problem due to the fact that the area of the single analog to digital converter of the array analog to digital converter is small is reduced to a great extent. According to the multi-way collaborative digital correction technology of the array analog to digital converter applied to the CMOS image sensor provided by the invention, the integral performance of the array analog to digital converter can be effectively improved.
Owner:JILIN UNIV

LED epitaxial wafer and preparation method thereof

PendingCN114725258AAvoid going too fastReduce warpage variationPolycrystalline material growthFrom chemically reactive gasesPhysicsEngineering
The invention provides an LED epitaxial wafer and a preparation method thereof, the LED epitaxial wafer comprises a substrate, and a low-temperature buffer layer, a three-dimensional growth layer, a two-dimensional growth layer and a GaN layer which are grown on the substrate in sequence, and the two-dimensional growth layer comprises a first sub-layer, a second sub-layer and a third sub-layer which are grown in sequence; wherein the first sub-layer is a periodic composite layer formed by repeatedly overlapping an AlGaN layer and a BGaN layer, the second sub-layer is a growth pause layer, and the third sub-layer is a periodic composite layer formed by repeatedly overlapping and growing a BN layer and an SiN layer. According to the LED epitaxial wafer, the two-dimensional growth layer is specially designed, and the composite two-dimensional growth layer is adopted, so that the LED epitaxial wafer which is higher in surface flatness, smaller in dislocation density, better in antistatic capacity, few in defect extending to a quantum well and improved in luminous intensity can be obtained.
Owner:JIANGXI ZHAO CHI SEMICON CO LTD

JPEG image mismatch steganography analysis method based on heterogeneous characteristic subspace migration

ActiveCN109348229ASmall discreteReduce the differenceDigital video signal modificationSteganalysisAugmented lagrange multiplier method
The invention relates to a JPEG image mismatch steganography analysis method based on heterogeneous characteristic subspace migration. The method provided by the invention takes characteristics of different fields as a combination of domain-independent and domain-related characteristic subspaces, and the method comprises the following steps: firstly providing a low-rank constrained domain-independent characteristic migration method, and realizing local information migration by utilizing local data characteristics between different fields; secondly, based on sparse representation of modeling domain-related characteristics, measuring influence produced by field change on the modeling domain-related characteristics; and finally, by virtue of the steps, constructing an objective function, andsolving by virtue of an imprecise augmented Lagrange multiplier method. Unique global information of the domain-related characteristics is considered while local information migration is realized in adomain-independent characteristic subspace, so that characteristic differentiation degree between a cover image and a stego image can be improved, detection effect of mismatch steganography analysiscan be beneficially improved, and great significance is produced to the mismatch steganography analysis.
Owner:WUHAN UNIV

ZnO-based nanorod/ quantum well composite ultraviolet light-emitting diode and preparation method thereof

ActiveCN106601884AAchieving pure UV electroluminescenceReduce Mismatch ProblemsSemiconductor devicesExciton binding energyQuantum well
The invention discloses a ZnO-based nanorod / quantum well composite ultraviolet light-emitting diode and a preparation method thereof. The light-emitting diode comprises a substrate. The substrate is provided with an n-type ZnO thin film layer, a ZnO nanorod array, a ZnO / Zn1-xMgxO quantum well active layer, a p-type NiO thin film layer and a first electrode from the bottom up in sequence. A second electrode and the ZnO nanorod array are arranged on the n-type ZnO thin film layer in parallel; and the ZnO / Zn1-xMgxO quantum well active layer covers the ZnO nanorod array, 0.1<=x<=0.3. The light-emitting diode electroluminescent peak wavelength is around 374 nm, and full width at half maximum of the photoluminescence peak is around 17 nm; the light-emitting diode structure can give full play to the advantages of direct broadband gap and high exciton binding energy of the ZnO material and the like, so that polarization effect is reduced effectively, material and interface quality can be improved, effective area of the active layer is increased, light extraction efficiency is improved and spectrum monochromaticity is improved; and besides, low-temperature preparation can be realized, cost is low and industrialization can be realized easily.
Owner:SOUTH CENTRAL UNIVERSITY FOR NATIONALITIES

Light emitting diode epitaxial wafer and preparation method thereof

The invention discloses a light emitting diode epitaxial wafer and a preparation method thereof, which belong to the field of light emitting diode manufacturing. The AlGaN sub-layers and the first GaNsub-layers which are alternately stacked can release certain stress in the growth process, and dislocation defects accumulated in the first composite layer are few. The buffer layer further comprisesa second composite layer stacked on the first composite layer, and the structure of the second composite layer can be a second GaN sub-layer and a MgN sub-layer which are alternately stacked, and a second GaN sub-layer and a BN sub-layer which are alternately stacked. The Mg atoms and B atoms in the BN sub-layer are small in particle size, vacancies generated by defects and dislocations in crystals can be filled in the growth process, so that the formation of the dislocations and the defects is reduced, the crystal quality of the buffer layer is improved, and the luminous efficiency of the finally obtained light-emitting diode epitaxial wafer is also improved.
Owner:HC SEMITEK ZHEJIANG CO LTD

Epitaxial structure of Si-based gallium nitride device

An epitaxial structure of a Si-based gallium nitride device belongs to the technical field of microelectronics. The epitaxial structure comprises a substrate, a nucleating layer, a buffer layer, a high-resistance layer, a channel layer and a barrier layer which are sequentially stacked from bottom to top, wherein the nucleating layer is formed by ALN / GaN cyclic growth, and the buffer layer is formed by InN / SiN / GaN in a cyclic growth mode and comprises an InN crystal nucleus layer, a reticular structure SiN thin layer and a GaN filling layer. According to the invention, the ALN / GaN nucleating layer is circularly grown to relieve lattice mismatch and thermal mismatch of the substrate and the epitaxial layer, and the InN / SiN / GaN buffer layer can greatly reduce the dislocation density of the material and improve the lattice quality, thereby improving the electron mobility, breakdown voltage, leakage current and other characteristics of the HEMT device.
Owner:西安电子科技大学芜湖研究院

Nitride epitaxial layer preparation method and semiconductor epitaxial wafer thereof

The invention discloses a nitride epitaxial layer preparation method and a semiconductor epitaxial wafer thereof. The method comprises the following steps: providing a substrate; a buffer layer is grown on the substrate, the buffer layer comprises a nitride buffer layer and an oxygen-containing buffer layer, and the nitride buffer layer and the oxygen-containing buffer layer are grown by alternately switching an MO source and an oxygen-containing MO source in a periodic cycle mode to serve as precursor materials; and growing a nitride epitaxial layer on the buffer layer. The oxygen-containing buffer layer is grown through the oxygen-containing MO source process, on one hand, the in-situ growth oxygen-containing buffer layer has good lattice mismatch relaxation, relieves lattice adaptation and releases the stress of the substrate and the epitaxial layer, and a high-quality gallium nitride epitaxial layer with low dislocation density can be obtained; the distribution uniformity and nucleation density of oxygen-containing buffer crystal grains are improved, and a high-quality nitride epitaxial layer is obtained; on the other hand, the technological process is simple, pollution risks in the substrate and epitaxial layer transfer process are reduced, repeatability is good, and large-scale production is facilitated.
Owner:JIANGSU INST OF ADVANCED SEMICON CO LTD

W type antimony-based semiconductor laser with gradually varied Ga In proportion

The invention relates to a W type antimony-based semiconductor laser with gradually varied Ga In proportion, which belongs to the technical field of semiconductor lasers. The existing InAs/GaInSb W type antimony-based semiconductor laser is difficult to realize luminescence at room temperature, and is less in output power of luminescence at low temperature (73K). The W type antimony-based semiconductor laser with gradually varied Ga In proportion sequentially comprises a GaSb substrate, a GaSb buffer layer, a P type GaSb contact layer, a P type quantum well, an intrinsic quantum well, an N type quantum well and an N type InAs contact layer from bottom to top, wherein the P type quantum well, the intrinsic quantum well and the N type quantum well respectively have a multi-period structure; the structure of each single-period quantum well in each multi-period structure is a sandwich structure that a GaInSb hole quantum well is clamped by double InAs electronic quantum wells; the outer layer is a pair of AlSb alloy limiting layers. The W type antimony-based semiconductor laser with gradually varied Ga In proportion is characterized in that the GaInSb hole quantum well is formed by 3 to 9 layers of Ga1-xInxSb layers, wherein x is equal to 0.05-0.35; the value of x of the Ga1-xInxSb layer in the middle is maximal; the Ga1-xInxSb layers on two sides are distributed in 1 to 4 levels from the middle to two sides; the values of x of two Ga1-xInxSb layers at the same level are the same, and the values of x of the Ga1-xInxSb layers from the middle to two sides are gradually reduced.
Owner:CHANGCHUN UNIV OF SCI & TECH

Epitaxial wafer of light-emitting diode and preparation method of epitaxial wafer

The invention discloses an epitaxial wafer of a light-emitting diode and a preparation method of the epitaxial wafer and belongs to the field of semiconductor optoelectronics. According to the method,an Al<x>Ga<1-x>N layer and an Al<y>Ga<1.5y>In<1-2.5y>N layer are sequentially arranged between an AlN layer and an undoped GaN layer, Al components in the Al<x>Ga<1-x>N layer and the Al<y>Ga<1.5y>In<1-2.5y>N layer can be within the ranges of 0.4<=x<=1 and 0.2<=y<=0.4, and when the Al components in the Al<x>Ga<1-x>N layer and the Al<y>Ga<1.5y>In<1-2.5y>N layer are within the ranges, lattice mismatch between the AlN layer and the undoped GaN layer can be relieved. Moreover, the Al component in the Al<x>Ga<1-x>N layer and the Al component in the Al<y>Ga<1.5y>In<1-2.5y>N layer are both graduallyreduced along the growing directions of the two layers, the Al components in the two layers are equal at the interface of the two layers, therefore, connection of the AlN layer and the undoped GaN layer can be well realized, defects generated due to lattice mismatch between the AlN layer and the undoped GaN layer are reduced, the crystal quality of the epitaxial wafer of the finally obtained light-emitting diode is improved, and the luminous efficiency of the finally obtained light-emitting diode is improved.
Owner:HC SEMITEK ZHEJIANG CO LTD

ZnO-based nanorod/quantum well composite ultraviolet light-emitting diode and preparation method thereof

ActiveCN106601884BAchieving pure UV electroluminescenceReduce Mismatch ProblemsSemiconductor devicesElectricityExciton binding energy
The invention discloses a ZnO-based nanorod / quantum well composite ultraviolet light-emitting diode and a preparation method thereof. The light-emitting diode comprises a substrate. The substrate is provided with an n-type ZnO thin film layer, a ZnO nanorod array, a ZnO / Zn1-xMgxO quantum well active layer, a p-type NiO thin film layer and a first electrode from the bottom up in sequence. A second electrode and the ZnO nanorod array are arranged on the n-type ZnO thin film layer in parallel; and the ZnO / Zn1-xMgxO quantum well active layer covers the ZnO nanorod array, 0.1<=x<=0.3. The light-emitting diode electroluminescent peak wavelength is around 374 nm, and full width at half maximum of the photoluminescence peak is around 17 nm; the light-emitting diode structure can give full play to the advantages of direct broadband gap and high exciton binding energy of the ZnO material and the like, so that polarization effect is reduced effectively, material and interface quality can be improved, effective area of the active layer is increased, light extraction efficiency is improved and spectrum monochromaticity is improved; and besides, low-temperature preparation can be realized, cost is low and industrialization can be realized easily.
Owner:SOUTH CENTRAL UNIVERSITY FOR NATIONALITIES

W-type antimony-based semiconductor laser with ga In ratio gradient

The invention relates to a W type antimony-based semiconductor laser with gradually varied Ga In proportion, which belongs to the technical field of semiconductor lasers. The existing InAs / GaInSb W type antimony-based semiconductor laser is difficult to realize luminescence at room temperature, and is less in output power of luminescence at low temperature (73K). The W type antimony-based semiconductor laser with gradually varied Ga In proportion sequentially comprises a GaSb substrate, a GaSb buffer layer, a P type GaSb contact layer, a P type quantum well, an intrinsic quantum well, an N type quantum well and an N type InAs contact layer from bottom to top, wherein the P type quantum well, the intrinsic quantum well and the N type quantum well respectively have a multi-period structure; the structure of each single-period quantum well in each multi-period structure is a sandwich structure that a GaInSb hole quantum well is clamped by double InAs electronic quantum wells; the outer layer is a pair of AlSb alloy limiting layers. The W type antimony-based semiconductor laser with gradually varied Ga In proportion is characterized in that the GaInSb hole quantum well is formed by 3 to 9 layers of Ga1-xInxSb layers, wherein x is equal to 0.05-0.35; the value of x of the Ga1-xInxSb layer in the middle is maximal; the Ga1-xInxSb layers on two sides are distributed in 1 to 4 levels from the middle to two sides; the values of x of two Ga1-xInxSb layers at the same level are the same, and the values of x of the Ga1-xInxSb layers from the middle to two sides are gradually reduced.
Owner:CHANGCHUN UNIV OF SCI & TECH

A gallium nitride-based light-emitting diode epitaxial wafer and its preparation method

The invention discloses a gallium nitride-based light emitting diode epitaxial wafer and a preparation method thereof and belongs to the technical field of a semiconductor. The gallium nitride-based light emitting diode epitaxial wafer includes a substrate, and a buffer layer, a quality improvement layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked on the substrate, wherein the material of the substrate is sapphire, the material of the N-type semiconductor layer, the active layer and the P-type semiconductor layer is a galliumnitride-based material, the quality improvement layer includes a first sub layer and a second sub layer which are sequentially stacked, the material of the first sub layer is non-doped aluminum gallium nitride, the material of the second sub-layer is non-doped aluminum indium nitride, and the aluminum component content of the first sub layer and the second sub layer gradually decreases along the stacking direction of gallium nitride-based light emitting diode epitaxial wafers. The method is advantaged in that crystal quality of the epitaxial wafer can be effectively improved, composite light emitting of carriers in an active layer is facilitated, and light emitting efficiency of LEDs is improved.
Owner:HC SEMITEK ZHEJIANG CO LTD
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