312results about How to "Improve operating speed" patented technology

Port Interface Modules (PIMs) are provided for ports of a Multi-Port Memory Controller. The PIMs include logic that is programmable to be compatible with different types of devices, processors or buses that can be connected to the ports. The PIMs can further include protocol bridges to enable one port PIM to connect to a device or another port PIM in a master/slave fashion.

The invention discloses an image enhancement and partition method, which comprises the following steps of I, image enhancement: a processor and an image enhancement method based on fuzzy logic are adopted for performing enhancement processing on an image needing to be processed, and the process is as follows: i, converting from an image domain to a fuzzy domain: mapping the grey value of each pixel point of the image needing to be processed to a fuzzy membership degree of a fuzzy set according to a membership function (shown in the specifications); ii, performing fuzzy enhancement processing by utilizing a fuzzy enhancement operator in the fuzzy domain; iii, converting from the fuzzy domain to the image domain; II, image partition: partitioning a digital image subjected to enhancement processing, i.e. a to-be-partition image, according to an image partition method based on a three-dimensional fuzzy division maximum entropy. The method is simple in steps, reasonable in design, convenient to realize, good in processing effect and high in practical value, and an image enhancement and partition process can be simply, conveniently and quickly completed with high quality.

A gravimetric dosing apparatus includes a support frame, a plurality of loading hoppers for a respective granular material to be dosed, carried by the support frame and provided with a respective discharge outlet and an opening-closing device for their respective discharge outlet. A weighing hopper includes a discharge outlet and an opening and closing device for its respective discharge outlet and arranged in cascade with respect to the loading hoppers to receive from at least two of the hoppers dosed quantities of different granular materials. A support element is articulated to the frame and designed to overhangingly support the weighing hopper. Transducing structure generates output signals proportional to the weight of the material discharged into the weighing hopper. A mixing assembly receives the dosed and weighed granular material, and a program control unit receives input signals from the transducer and program controls the opening-closing devices.

The present invention provides a liquid crystal display device that achieves increase in operating speed of a drive circuit, reduction in load of signal source, low power consumption, and improvement in reliability of electric conduction between a liquid crystal display section and a liquid crystal driver. The liquid crystal display device includes a liquid crystal display section 44, a source driver 30 having an input latch circuit 48 and circuits 33 to 37, and 39 each of which samples gradation displaying data signal R,G, or B outputted from a control circuit 45 and holds the signal in output terminals thereof for a predetermined period. The circuits 33 to 37, and 39 are each formed of a p-Si thin film on a glass substrate 43 on which the liquid crystal display section 44 is provided. Moreover, the input latch circuit 48 is formed inside a logic circuit 41 formed on a monocrystal silicon substrate.

A trainer control method is provided and includes mounting a sensor at a user's upper extremity, sending from the sensor a sensing signal variable with the position or motion of the upper extremity, and controlling the operating speed of a trainer by the user according to the upper extremity, wherein the sensing signal causes the trainer operating speed to increase and decrease whenever the upper extremity is in first and second states for predetermined duration, respectively. Accordingly, riot only does the user control the operating speed and state of the trainer easily, but user safety is also enhanced.

A volatile memory element and a nonvolatile memory element, each of which is constituted of a field effect transistor, are formed on a single semiconductor chip. The volatile memory element includes a body region, a gate electrode, and two diffusion layer regions, and varies an amount of a current, flowing between the diffusion layer regions in applying a voltage to a gate electrode, in accordance with an amount of electric charge retained in the body region. The nonvolatile memory element includes diffusion layer regions, a gate electrode, and two memory function sections, and varies an amount of a current, flowing between the diffusion layer regions in applying a voltage to the gate electrode, in accordance with an amount of electric charge retained in the memory function sections. Thus, it is possible to form the volatile memory and the nonvolatile memory on a single chip with a simple process.

The invention discloses a multi-vehicle target identification method based on an improved YOLOv2 model, and the method comprises the steps: firstly collecting sample data in an actual traffic environment, and dividing the sample data into sample images of a training set and a test set according to a proportion of 7: 3; then performing data enhancement on the training set sample images, including random scaling of the sample images and adjustment of exposure and saturation so that the processed images are enabled to act as the input of the training model; carrying out target area feature vectorextraction on the processed training set through an improved Darknet-19 network; inputting the training set into a Darknet-19 network model for training to obtain a detection and recognition model; and finally, inputting the test set into the model for testing to obtain a multi-target vehicle identification result. According to the method, the problems of low detection rate, poor robustness and non-ideal classification effect of a road vehicle multi-target detection and vehicle type classification method in the prior art are solved.

A method, apparatus, and full-system simulator for speeding memory management unit simulation with direct address mapping on a host system, the host system supporting a full-system simulator, on which a guest system is simulated, the method comprising the following steps: setting a border in the logical space assigned for the full-system simulator by the host system, thereby dividing the logical space into a safe region and a simulator occupying region; shifting the full-system simulator itself from the occupied original host logical space to the simulator occupying region; and reserving the safe region for use with at least part of the guest system.

A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme.

An analog-digital delta-sigma converter includes a plurality of continuous time integrators for performing a delta-sigma modulation. Each integrator includes at least one charge sharing integrator at a modulator input. One or more pure integrators follow the charge sharing integrator.

The invention discloses a planar waveguide type near-and-mid infrared light modulator based on graphene-chalcogenide glass, and belongs to the technical field of electro-optical modulators. The optical modulator solves the problems in modulation and demodulation of integrated photonic devices based on optical signals of near-and-mid infrared light ranging from 1.55 microns to 3 microns. The modulator comprises a substrate layer, ridge-shaped light waveguide layers, a first strut and a second strut, wherein the ridge-shaped light waveguide layers, the first strut and the second strut are arranged on the substrate layer; a first graphene layer and a second graphene layer are arranged on the ridge-shaped light waveguide layers; the first graphene layer extends to the upper surface of the first strut, and the second graphene layer extends to the upper surface of the second strut; isolation medium layers are arranged between the ridge-shaped optical waveguide layer and the first graphene layer, between the ridge-shaped optical waveguide layer and the second graphene layer, between the first graphene layer and the second graphene layer, between the first graphene layer and the first strut, and between the second graphene layer and the second strut respectively; a first electrode is arranged on the first graphene layer on the first strut, and a second electrode is arranged on the second graphene layer on the second strut. The modulator is used for signal modulation and demodulation in the integrated photonic devices.

Provided is a membrane filtration system which makes it possible to improve operation rate of the system by increasing the amount of water to be treated, and to reduce costs required for chemical washing and replacement of a membrane. Accordingly, a total running cost is reduced. The membrane filtration system is provided with temperature-responsive membrane modules for filtering supplied raw water to discharge it as treated water. In each of the temperature-responsive membrane modules, temperature-responsive membranes are formed into any one of planar and cylindrical forms, and are then filled into a container.

Provided is an organic macromolecule resistance memory structure unit, comprising an insulating substrate (1), a bottom electrode layer (2), a resistance memory layer (3) and a top electrode layer (4). The resistance memory layer (3) is consisted of an organic macromolecule electrolyte material (6) and an organic macromolecule resistance variable material (5). The organic macromolecule resistance memory structure unit is stimulated with a pulse voltage or a scan voltage, when stimulating, removing the stimulate and re-stimulating, the current-stimulate times characteristic curve and current-time characteristic curve are represented a character like the biology neuron synapse which realizes learning, memory, forgetting, recalling. The organic macromolecule resistance memory structure unit can be used to the computer field as an new type microelectronics-bionics units by simulating the working mode of human brain neuron synapse dealing and learning information, so the calculation speed and process ability in parallel of the computer will be increased greatly.