A synchronous
DRAM and method are provided in which main cells and spare cells are accessed by an external address during automatic refresh of a test mode. In the synchronous
DRAM, a mode register setting circuit receives an external
signal in response to a plurality of control signals to generate a mode register setting
signal, during an automatic refresh operation in a test mode. An address selector selects and outputs an external address to the
memory cell array, in response to the activation of the mode register set
signal, during the automatic refresh operation in the test mode. The address selector selects and outputs an internal address to the
memory cell array, in response to the deactivation of the mode register set signal, during an automatic refresh operation in a
normal mode. Therefore, the main cells and the spare cells in the
memory cell array are sequentially accessed and refreshed by the external address during the automatic refresh operation in the test mode.< / PTEXT>