An integrated
memory controller (IMC) including MemoryF / X Technology which includes
data compression and decompression engines for
improved performance. The
memory controller (IMC) of the present invention preferably selectively uses a combination of lossless, lossy, and no compression
modes. Data transfers to and from the integrated
memory controller of the present invention can thus be in a plurality of formats, these being compressed or normal (non-compressed), compressed lossy or lossless, or compressed with a combination of lossy and lossless. The invention also indicates preferred methods for specific compression and decompression of particular data formats such as
digital video, 3D textures and image data using a combination of novel lossy and
lossless compression algorithms in block or span addressable formats. To improve latency and reduce performance degradations normally associated with compression and decompression techniques, the MemoryF / X Technology encompasses multiple novel techniques such as: 1) parallel
lossless compression / decompression; 2) selectable compression
modes such as lossless, lossy or no compression; 3) priority compression mode; 4)
data cache techniques; 5) variable compression block sizes; 6) compression reordering; and 7) unique address translation, attribute, and address caches. The
parallel compression and decompression
algorithm allows high-speed
parallel compression and high speed parallel
decompression operation. The IMC also preferably uses a special memory allocation and
directory technique for reduction of table size and low latency operation. The integrated
data compression and decompression capabilities of the IMC remove
system bottle-necks and increase performance. This allows lower cost systems due to smaller data storage, reduced bandwidth requirements, reduced power and
noise.