494 results about "Hybrid integrated circuit" patented technology

To provide a technology, which enable carrying out an optical position alignment precisely and easily in apparatus and the like used in optical communication, a method of manufacturing an optical module includes forming a guide pin in either a transparent substrate or an optical transmission line support member; forming a guide hole, in which the guide pin is to be inserted, to the other one of the transparent substrate and the optical transmission line support member such that the diameter of the guide hole is made larger as compared with the diameter of the hole; arranging a jig having a protruding portion, of which diameter is substantially the same as the diameter of the guide pin, over the transparent substrate such that the protruding portion is being inserted into the guide hole; filling the gap between the protruding portion and the guide hole with a filler material, which is cured by carrying out a predetermined processing; adjusting a position of the jig; curing the filler material, which is filled in the gap between the protruding portion and the guide pin; and pulling out the protruding portion from the guide hole.

To provide a thin metal base circuit board which can be not only installed on a flat portion but also closely attached to a side or bottom surface of a case or to a stepped or curved portion and which is excellent in heat dissipation performance, electrical insulating performance and flexibility; a process for its production; and a hybrid integrated circuit, an LED module and a bright, ultra-long-life LED light source employing it.A metal base circuit board having insulating layers and conductive circuits or metal foils alternately laminated, characterized in that the thickness of each conductive circuit or metal foil is from 5 μm to 450 μm, each insulating layer is made of a cured product of a resin composition comprising an inorganic filler and a thermosetting resin, and the thickness of each insulating layer is from 9 μm to 300 μm; and a hybrid circuit board employing it. The metal base circuit board wherein a coverlay is provided, and a layer having a magnetic loss or a layer having a dielectric loss is laminated on the surface of the coverlay. A LED light source unit having at least one light-emitting diode (LED) mounted on the conductive circuit.

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and this top surface is in turn electrically coupled to a front surface of an input / output (I / O) integrated circuit that faces the top surface. Furthermore, the front surface of the I / O integrated circuit is electrically coupled to a top surface of the optical integrated circuit, where the top surface of the optical integrated circuit faces the front surface of the I / O integrated circuit.

An opto-electronic hybrid integrated circuit of the present invention satisfy a low-loss optical waveguide function, an optical bench function and a high-frequency electrical wiring function. The circuit includes a substrate such as a silicon substrate, a dielectric optical waveguide part arranged in a recess of the substrate, and an optical device mounting part formed on a protrusion of the substrate. An electrical wiring part is disposed on the dielectric layer. The optical device is mounted on the substrate. An optical sub-module includes the optical device which is possible to mount on the substrate.

An improved hybrid integrated circuit is provided in order that the specification can quickly be modified and adjusted when required without need for preparing a new mask and without need for compromising the performance of the hybrid integrated circuit. The hybrid integrated circuit comprises: a common substrate on which an electrode pattern is formed; a first monolithic semiconductor chip designed by the use of an ASIC technology and mounted on the common substrate; a second monolithic semiconductor chip designed by the use of an FPGA technology and mounted on the common substrate; and external terminals provided for the common substrate; and an insulating material encapsulating the first monolithic semiconductor chip and the second monolithic semiconductor chip, wherein the second monolithic semiconductor chip is provided with a storage element which is rewritable by means of a control signal given through the external terminal in order to store circuit configuration data with which internal connections of the second monolithic semiconductor chip are modified to form a hardware configuration within the second monolithic semiconductor chip corresponding to a predetermined operational specification, and wherein the first monolithic semiconductor chip and the second monolithic semiconductor chip cooperate with each other by exchanging signals through the electrode pattern of the common substrate in order to implement the predetermined operational specification.

The present invention describes a hybrid integrated circuit comprising both CMOS and III-V devices, monolithically integrated in a single chip. It allows the almost complete elimination of the contamination issues related to the integration of different technologies, maintaining at the same time a good planarization of the structure. It further simplifies the fabrication process, allowing the growth of high quality III-V materials on (100) silicon substrates lowering the manufacturing cost. Moreover, differently from many prior art attempts, it does not require silicon on insulator technologies and / or other expensive process steps. This invention enables the consolidation on the same integrated circuit of a hybrid switching power converter that takes advantage of the established circuit topologies of CMOS circuitries and of the higher mobility and voltage withstanding of III-V HEMT devices.

To provide an optical module capable of miniaturization, the optical module, to which an optical plug provided at one end of an optical transmission path is attached, so as to transmit and receive signal light via the optical transmission path for information communication, includes: a transparent substrate having light transmittance property with respect to a wavelength of used signal light; an optical socket, which is arranged on one surface side of the transparent substrate and to which the optical plug is attached; an optical element, which is arranged on the other surface side of the transparent substrate and emits the signal light to the one surface side of the transparent substrate according to a supplied electrical signal, or generates an electrical signal according to the intensity of the signal light supplied from the other surface of the transparent substrate; and a reflective portion, which is arranged on the other surface of the transparent substrate and changes a path of the signal light emitted from the optical element at substantially 90 degrees to guide it to the optical transmission path, or changes a path of the signal light emitted from the optical transmission path at substantially 90 degrees to guide it to the optical element.

The invention discloses a field programmable gate array (FPGA)-based integrated circuit testing system, and a method for testing a digital-analog hybrid integrated circuit chip provided with a digital module or using a digital module as a main module and provided with a few analog modules by using the testing system. The system mainly comprises a personal computer (PC) machine, a main control chip, a FPGA chip, configuration information storage equipment and testing vector storage equipment. The testing method is implemented by the following steps that: the main control chip configures the FPGA chip, the main control chip sends a testing command to the FPGA chip, the FPGA chip sends an excitation signal to a chip to be tested and acquires the output response of the chip to be tested, or the analog parameter module acquires analog output response, the FPGA chip compares the output response or the analog output response of the chip to be tested with the testing information and judges the consistency of the output response and the testing information, and the chip to be tested is an accepted product or a defective product is judged. The system and the method can be widely applied in the field of integrated circuit chip test.

Provided is a circuit device, in which circuit elements incorporated are electrically connected to each other via a lead so as to achieve both of the enhanced functionality and miniaturization. In a hybrid integrated circuit device, a first circuit board and a second circuit board are incorporated into a case member in a way that a first circuit board is overlaid with a second circuit board. A first circuit element is arranged on the upper face of the first circuit board and a second circuit element is arranged on the upper face of the second circuit board. Leads provided in the hybrid integrated circuit device include a lead connected only to the first circuit element mounted on the first circuit board, a lead connected only to the second circuit element mounted on the second circuit board, and a lead connected to both of the first circuit element and the second circuit element.

Provided is a circuit device capable of increasing the packaging density and also suppressing the thermal interference between incorporated circuit elements. In a hybrid integrated circuit device, a first circuit board and a second circuit board are incorporated into a case member being arranged in a way that the first circuit board is overlaid with the second circuit board. A first circuit element is arranged on the upper face of the first circuit board and a second circuit element is arranged on the upper face of the second circuit board. In addition, inside the case member, a hollow portion (internal space) which is not filled with a sealing resin is provided, and this hollow portion communicates with the outside through a communicating opening, which is provided by partially opening the case member.

A chip package includes an integrated circuit and an optical integrated circuit (such as a hybrid integrated circuit) with an optical source and / or an optical receiver. The integrated circuit and the optical integrated circuit may be proximate to each other on opposite sides of an interposer in the chip package. Moreover, the integrated circuit may include a driver circuit of electrical signals for the optical source and / or a receiver circuit of electrical signals from the optical receiver. Furthermore, the optical integrated circuit may be positioned in a hole or an etch pit in a substrate, and an alignment feature may mechanically couple the substrate to an optical-fiber assembly, so that the optical-fiber assembly is positioned relative to the interposer and the optical integrated circuit. In particular, the optical-fiber assembly may partially overlap the interposer, so that optical signals are provided and / or received from the optical integrated circuit through the interposer.

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits that modulate data, communicate data, and serialize / deserialize data, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and a top surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit. Furthermore, a bottom surface of the optical integrated circuit faces the top surface of the interposer, and the front surface of the optical integrated circuit is optically coupled to an optical-fiber receptacle, which in turn is optically coupled to an optical-fiber connector.

A circuit device suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, and a manufacturing method thereof are provided. According to a hybrid integrated circuit device of the present invention and a manufacturing method thereof, a first conductive film is laminated on a first insulating layer, and a first wiring layer is formed by patterning the first conductive film. Next, a second conductive film is laminated on a second insulating layer. Thereafter, by partially removing the second insulating layer and the second conductive film in a desired spot, a connection part for connecting the wiring layers to each other is formed.

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each other on the same side of a substrate in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. In addition, an input / output (I / O) integrated circuit is coupled to the optical integrated circuit between the substrate and the optical integrated circuit. This I / O integrated circuit includes high-speed I / O circuits and energy-efficient driver and receiver circuits and communicates with optical devices on the optical integrated circuit. By integrating the optical integrated circuit, the integrated circuit and the I / O integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC.

A composite silicon aluminocarbide material or its member is prepared through preparing the aluminum phosphate solution from phosphoric acid and aluminum hydroxide, mixing it with polyethanediol, distilled water, dextrin and glutinous rice flour to obtain binder, mixing it with silicon carbide microparticles, die pressing to obtain prefabricated raw material, heat treating in inertial gas or air, pressure casting or vacuum impregnating to osmosize the molten aluminum alloy into it, and machining by needed sizes. Its advantages are low density, adjustable expansibility, high thermal conductivity, elastic modulus and air tightness.

The invention discloses a bonding system of a high-reliability thick-film mixed integrated circuit and a manufacturing method thereof. The system and the method are characterized in that the bonding system is an indirectly bonded bonding system, namely, a layer of blocking layer metal film is added on the surface of the metal bonding area and a layer of metal film capable of carrying out high-reliability bonding with the silicon-aluminium wire is then added on the surface of the metal bonding area so as to form a multilayer transitional film; and subsequently the bonding system of the silicon-aluminium wire is carried out on the surface of the metal bonding area. The system and the method have the advantages of: (1) improving the bonding performance of the bonding area of the thick-film gold conducting belt and the silicon-aluminium wire; (2) forming local nickel bonding area or an aluminium bonding area on the bonding area of the same gold conducting belt, and being compatible with the gold wire bonding and silicon-aluminium wire bonding; and (3) adopting a metal mask location register and high-vacuum deposition film-formation technology and having no damaging effects on the substrate of the thick-film. When being applied to all thick-film mixed integrated circuit taking gold conducting belts or silver conducting belts as substrates, the reliability of the mixed integrated circuit can be improved and the mixed integrated circuit has wide application prospect in the fields such as aviation, spaceflight, navigation, communication, industrial control and the like.

In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu / Sn alloy layer having poor soldering properties is not generated but a Ni / Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.

The invention relates to the field of digital-analog hybrid integrated circuit design, aims to increase the conversion rate of a monoclinic ADC and provides the analog-digital converter which is simple in structure and low in power consumption. According to the adopted technical scheme of a low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and a converter, the converter is composed of a ramp generator, a counter, comparators, multiplexer switches and a register; the ramp generator generates a ramp voltage Vramp and k reference voltages VrefK, wherein K=1, 2, 3..., K; each of the k reference voltages VrefK is supplied to the corresponding comparator through one of the corresponding multiplexer switches; the ramp voltage Vramp is supplied to each comparator. The low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and the converter are mainly applied to digital-analog hybrid integrated circuit design.

A hybrid integrated circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed input and output buffer circuits, and a first group of input / output pads, wherein one of the input / output pads of the first group is connected to an input of one of the input buffer circuits, and one of the input / output pads of the first group is connected to an output of one of the output buffer circuits. The field programmable gate array portion has programmable digital logic function modules, a second group of input / output pads, interconnect conductors divided into one or more segments, wherein some segments run in a first direction and some segments run in a second direction to form intersections and some segments form intersections with inputs and outputs of the digital logic function modules, the first group of input / output pads, and inputs and outputs of the output and input buffer circuits from the mask programmable portion, and user programmable interconnect elements connected between adjoining ones of the segments in a same one of the interconnect conductors, and between intersections of selected ones the first and second segments, intersections of inputs and outputs of the digital logic function modules and selected interconnect conductors, intersections of the first group of input / output pads and selected ones of the interconnect conductors, intersections with outputs of the input buffer circuits and selected ones of the interconnect conductors, and intersections with the inputs of the output buffer circuits and selected ones of the interconnect conductors.

The invention provides preparation methods of aluminium silicon carbide composites with interpenetrating network structure and components of the composites. The composites are used for electronic packaging. The composites or the components of the composites comprise the following raw materials by volume: 45-85% of reinforcing phase silicon carbide and 15-55% of aluminium matrix, and at the same time, the reinforcing phase silicon carbide and the aluminium matrix form the interpenetrating network structure. The preparation methods comprise the following steps: firstly preparing silicon carbide preform bisques and keeping the silicon carbide preform bisques at the constant temperature of about 2200 DEG C for 1-3 hours under the protection of argon to obtain silicon carbide preforms with network structure; infiltrating aluminium alloy liquid into the pores of the preforms by adopting a vacuum pressure infiltration process to prepare the aluminium silicon carbide composites with interpenetrating network structure or components or near-net-shaped components; and finally obtaining the components with final shapes and dimensions through machining. Through the preparation methods, the products have the characteristics of adjustable coefficient of expansion, higher heat conductivity, higher elastic modulus, good air tightness and low cost and can be applied in the field of packaging of such electronic devices as hybrid integrated circuits, millimeter wave / micron wave integrated circuits, multichip modules, large current power modules and the like.

The invention discloses a laser unsealing method. The method includes the steps that positions and depths of all elements and a chip in a plastic package device are positioned to obtain size, position and depth information of the elements and the chip in the device; according to the information, a preset unsealing area of the plastic package device is determined for unsealing and positioning; laser ablation is conducted on the plastic package device in a cross filling mode to remove molding materials on the surface of the plastic package device, so that inner lead bonding wires are just exposed out of a chip area, tin-lead welding points are just exposed near a resistor and a capacitor, and inductance is just exposed near an inductor. Acidic liquid is adopted to corrode a molding compound covering the chip till the chip is exposed. The method can well solve the problem that a traditional method can not unseal a plastic mixed integrated circuit easily, and effectively increases the unsealing success rate of the plastic package device.

The invention discloses a plastic package device opening method. The plastic package device opening method comprises positioning the positions and the depths of various elements inside a plastic package device to obtain the size, position and depth information of the various elements and the chip inside the device; opening the plastic package device through a laser ablation method to remove package materials on the surface of the plastic package device to exactly expose internal lead bonding wires in a chip area, tin-lead solder spots adjacent to a resistance capacitor, and an inductor adjacent to the inductor; masking the ablated plastic package device to mask the area not requiring corrosion with aluminum foils, and performing local corrosion on the masked plastic package device through corrosives. The plastic package device opening method can help precisely control the opening depth of every local area of the plastic package device and the properties of the corrosives, achieve precise multi-spot and layer-by-layer opening control effects and well solve the problem that traditional methods cannot easily open plastic package mixed integrated circuits.

The invention discloses a substrate integrated waveguide split ring resonator-based microwave band pass filter. The microwave band pass filter comprises a substrate integrated waveguide which is formed by fixing two rows of metal members on a dielectric substrate, wherein the two ends of the substrate integrated waveguide are connected with a micro-strip feed line respectively; the surfaces of both the micro-strip feed line and the substrate integrated waveguide are made of metal dielectric; the upper surface of the substrate integrated waveguide is positioned between the two rows of metal members to corrode an m*n split ring resonator array; and a row of dumbbell-shaped area bodies or dumbbell-shaped deformation areas are corroded corresponding to each line of split ring resonators on the lower surface of the substrate integrated waveguide between the two rows of metal members. The band pass filter has the advantages of out-of-band steep attenuation, small volume, light weight and high power capacity and is easy to be integrated with other planar microwave and millimeter-wave circuits, so that the band pass filter is expected to be applied to the microwave and millimeter-wave integrated circuit or a millimeter wave integrated circuit.