84 results about "Dielectric matrix" patented technology

An electrical interconnect system employs electrical connectors in which the contacts are identical for both the male and the female side of the connection. Contacts are arranged in a linear header and multiple header pairs are arranged in a dielectric matrix or grid. The grid is an external dielectric frame capable of providing load bearing and geometry requirements. This arrangement results in a cost-effective construction that features very high electrical bandwidth capabilities and an extremely rugged product.

Formulations for voltage switchable dielectric materials include two or more different types of semiconductive materials uniformly dispersed within a dielectric matrix material. The semiconductive materials are selected to have different bandgap energies in order to provide the voltage switchable dielectric material with a stepped voltage response. The semiconductive materials can comprise inorganic particles, organic particles, or an organic material that is soluble in, or miscible with, the dielectric matrix material. Formulations optionally can also include electrically conductive materials. At least one of the conductive or semiconductive materials in a formulation can comprise particles characterized by an aspect ratio of at least 3 or greater.

This invention is related to a reactive nanoparticular cyclodextrin derivative useful as a porogen and a low dielectric matrix, with excellent mechanical properties and uniformly distributed nanopores, manufactured by sol-gel reaction of the above reactive cyclodextrin. Furthermore, this invention also is related to an ultralow dielectric film, with uniformly distributed nanopores, a relatively high porosity of 51%, and a relatively low dielectric constant of 1.6, manufactured by thin-filming of the conventional organic or inorganic silicate precursor by using the above reactive nanoparticular cyclodextrin derivative as a porogen.

The invention relates to a method and a device (1) for combined current limitation and power breaking and to a switchgear having said device (1). In a combined current limiter / power braker (1) according to the invention, a movable electrode (3, 3') is guided automatically along a resistance element (5) for the current limiting path (31) by an overcurrent-dependent force (Fmag) for the purpose of current limitation and brought to an insulator (8) in a serial arrangement for power breaking purposes. Examples of embodiments are, inter alia, the utilization of Lorenz force for automatic current limitation; movable electrodes (3, 3') realized by means of liquid metal (3) or a movable solid conductor (3'); an electrical resistance (RX) increasing non-linearly in the direction of movement (x) for smooth power limitation characteristics and a resistance element (5) in the form of a dielectric matrix (5) with several channels (3a) for the liquid metal (3). Amongst the advantages achieved are electric arc-free, reversible current limitation and power breaking, which is also suitable for high voltages and currents, rapid reaction times, little wear and easy maintenance.

An anisotropic electrically conductive structure comprising: a dielectric matrix having a first surface and a second surface; a heat curable adhesive layer disposed on at least one or both of said first surface and said second surface; a plurality of passages at least extending from said first surface of said matrix to said second surface of said matrix; and electrically conductive members in said passages; wherein said dielectric matrix does not exhibit thermal fluidization at a temperature required for heat curing of said heat curable adhesive layer.

A method to make magnetic random access memory (MRAM), in particular, perpendicular spin transfer torque MRAM or p-STT-MRAIVI is provided. Electrically isolated memory cell is formed by ion implantation instead of etching and dielectric refill. Oxygen ion implantation is used to convert the photolithography exposed areas into metal oxide dielectric matrix. An ultrathin single-layer or multiple-layer of oxygen-getter, selected from Mg, Zr, Y, Th, Ti, Al, Ba is inserted into the active magnetic memory layer in addition to putting a thicker such material above and below the memory layer to effectively capture the impinged oxygen ions. Oxygen is further confined within the core device layer by adding oxygen stopping layer below the bottom oxygen-getter. After a high temperature anneal, a uniformly distributed and electrically insulated metal oxide dielectric is formed across the middle device layer outside the photolithography protected device area, thus forming MRAM cell without any physical deformation and damage at the device boundary.

Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

A capacitor (110), wherein the capacitor (110) comprises a capacitor dielectric (112) comprising a dielectric matrix (114) of a first value of permittivity, and a plurality of nanoclusters (116) of a second value of permittivity which is larger than the first value of permittivity which are at least partially embedded in the dielectric matrix (114), wherein the plurality of nanoclusters (116) are formed in the dielectric matrix (114) by spontaneous nucleation.