92results about How to "Reduce Capacitive Coupling" patented technology

Touch sensor panel configurations and methods for improving touch sensitivity of some or all of the electrodes or portions of the touch sensor panel are disclosed. The touch sensor panel configurations can allow increased speed at which the panel can operate. In some examples, the performance of a given touch electrode can differ from the performance of another touch electrode due to differences in capacitance and/or resistance. The performance of the touch sensor panel can be limited by the touch electrode with the lowest performance relative to the other touch electrodes. The configurations and methods can increase the performance of the touch sensor panel by minimizing the capacitive coupling and/or resistance of touch electrodes. Examples of the disclosure can provide configurations of touch sensor panels and methods for improving optical uniformity of the panel.

The embodiment of the invention discloses a display panel and a display device. The display panel comprises a display module and a fingerprint identification module, wherein the display module comprises a substrate base plate, a plurality of pixel units positioned on one side of the substrate base plate, and first scanning lines extending along the first direction, each pixel unit comprises a pixel drive unit and a light-emitting unit positioned on the side, far away from the substrate base plate, of the pixel drive unit, and the light-emitting unit comprises a metal anode; the fingerprint identification module is used for carrying out fingerprint identification according to light rays reflected to a fingerprint identification unit through a touch main body; the vertical projection of thefirst scanning lines on the substrate base plate and the vertical projection of the metal anode on the substrate base plate have an overlapped area. For the display panel provided by the embodiment ofthe invention, shielding electrodes are arranged between the film layer where the first scanning lines are located and the film layer where drain electrodes are located, the shielding electrodes andthe drain electrodes are insulated, the vertical projection of the shielding electrodes on the substrate base plate and the overlapped area are overlapped, the capacity coupling between the metal anode and the first scanning lines can be reduced, and thus the image display effect is improved.

The invention discloses an inductance coupling coil, which comprises at least two groups of mutually nested coil windings with different diameters, wherein the upper surfaces of at least two groups of the coil windings in the coil windings are at planes with different heights for the convenience of obtaining plasmas which are distributed evenly. Besides, the invention also discloses a plasma processing device comprising a reaction chamber; a dielectric window is arranged on the upper part of the reaction chamber, and the inductance coupling coil is arranged above the dielectric window; and the inductance coupling coil is connected with a radio frequency power supply through a radio frequency matcher so as to obtain the plasmas distributed evenly in the reaction chamber. The inductance coupling coil and the plasma processing device can obtain the plasmas which are distributed evenly, and can obtain an excellent and even processing/handling result.

A set of non-volatile storage elements undergoes initial programming, after which a reprogramming, with higher verify levels, is performed in non-real time, such as when a control enters a standby mode, when no other read or write tasks are pending. The reprogramming can program pages in the set one at a time, stopping at a page boundary when another read or write task is pending, and restarting when the control become available again. Status flags can be provided to identify whether a page and/or the set has completed the reprogramming. In another aspect, a higher pass voltage is applied to unselected word lines during the reprogramming. In another aspect, an error count is determined using a default set of read voltages, and an alternative set of read voltages is selected if the count exceeds a threshold.

The invention discloses a preparation method for a high-density interposer for microelectronic system-in-package. The preparation method comprises the following steps of: 1, preparing a drectionally growing carbon nanotube bundle array, wherein the diameter of each carbon nanotube bundle is 0.5 to 30 microns, the gap of the carbon nanotube bundle is 0.8 to 100 microns, and the carbon nanotube bundle is 40 to 500 microns long; 2, depositing metal tungsten on the surface of the drectionally growing carbon nanotube bundle so as to form a conductor array; 3, melting borosilicate glass and compounding the melted borosilicate glass with the conductor array so as to form a compound body; and 4, grinding the upper surface and the lower surface of the formed compound body so as to expose the end of the carbon nanotube bundle deposited with the metal tungsten, and obtaining the high-density interposer for the system-in-package. The material adopted by the preparation method has low thermal expansivity and the process method is low in time consumption, so the prepared high-density interposer has the advantages of high density, high reliability and low cost.

A semiconductor device has an RF balun formed over a substrate. The RF balun includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device. A first capacitor is coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The first conductive trace is formed completely within the second conductive trace. The first conductive trace and second conductive trace can have an oval, circular, or polygonal shape separated by 50 micrometers. A second capacitor is coupled between the first and second ends of the second conductive trace.

A surface acoustic wave device and a boundary acoustic wave device capable of reducing capacitive coupling are provided. A piezoelectric substrate (12) is joined to a cover (32) with a support layer 30 therebetween and with a spacing kept therebetween. A transmission surface acoustic wave filter and a reception surface acoustic wave filter are formed on a major surface (14) of the piezoelectric substrate (12) adjacent to the cover (32) and inside the support layer (30). External electrodes (28) are provided on the side of the cover (32) opposite that facing the piezoelectric substrate (12).; The external electrodes (28) include an antenna terminal electrically connected to the transmission surface acoustic wave filter and the reception surface acoustic wave filter, a transmission input terminal electrically connected to the transmission surface acoustic wave filter, and a reception output terminal electrically connected to the reception surface acoustic wave filter. Part of an interconnection line that electrically connects the reception surface acoustic wave filter to the antenna terminal is disposed on the cover (32).

The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In one embodiment, the transistor device is interconnected with gate fingers on a lower metaliization level, typically the first level metal, with the drain interconnected at a higher metal level. That allows the drain fingers to be cross-connected with a vertical separation between drain and gate comb electrodes. The cross-connect members may be further stabilized by adding beam extensions to the cross-connect members. The beam extensions may be anchored in an interlevel dielectric layer for additional support.

The invention relates to a thin-film-transistor array substrate and a forming method thereof. The array substrate comprises an insulating base, a first metal layer, a grid insulting layer, a noncrystalline silicon layer, a first conducting transparent material layer, a doped noncrystalline silicon layer, a second metal layer, a passivated layer and a second conducting transparent material layer, wherein the first metal layer is positioned above the insulating base, and a first part of the first metal layer forms a TFT grid which is electrically connected with a scanning line; the grid insulating layer is covered above the first metal layer and the insulating base; the noncrystalline silicon layer and the first conducting transparent material layer are both positioned above the grid insulating layer; the doped noncrystalline silicon layer is positioned above the noncrystalline silicon layer and forms a TFT semiconductor layer together with the noncrystalline silicon layer; the second metal layer is positioned above the doped noncrystalline silicon layer and the first conducting transparent material layer, a first part of the second metal layer forms a source electrode and a drain electrode of the TFT, and the source electrode is electrically connected with a data wire; the passivated layer is positioned above the second metal layer and is used as an insulator; the second conducting transparent material layer is positioned above the passivated layer, and a first part of the second conducting transparent material layer forms a pixel electrode connected with the drain electrode; and the first conducting transparent material layer forms part of a common electrode.

A sensor element, in particular a planar gas sensor element, having a sensor structure is described, which is heatable by a heater structure. A first spacer layer is provided between the heater structure and the sensor structure, the spacer layer having a first recess in the area of the heater structure into which a first inlay, which electrically insulates the heater structure from the sensor structure, is inserted.

The invention discloses a plasma processing device. The plasma processing device comprises an air-tight reaction chamber, wherein the reaction chamber comprises a reaction chamber sidewall and a top insulating material window, and the reaction chamber therein comprises a base for supporting a substrate to be processed; a self-shielding inductive coil group is fixedly arranged above the insulating material window. The plasma processing device is characterized in that the self-shielding inductive coil group comprises a plurality of inductive coils, each inductive coil comprises a flat-plate-shaped intermediate coil, a plurality of intermediate coils are combined to form a shielding ring, the two ends of each intermediate coil respectively comprise an input coil and an output coil, wherein the input coil and the output coil are spirally upward from the two ends of the intermediate coil and are respectively connected to a radio-frequency power supply and a regulating circuit, and downward projections of the input coil and the output coil are located on at least one intermediate coil. By adopting the inductive coil structure disclosed by the invention, the capacity coupling of the inductive coil towards the inside of the reaction chamber can be reduced and the service life of the insulating material window can be improved.

A microfabricated optical apparatus that includes a light source driven by a waveform, wherein the waveform is delivered to the light source by at least one through silicon via. The microfabricated optical apparatus may also include a light-sensitive receiver which generates an electrical signal in response to an optical signal. An optical source may be attached to a carrier substrate with the TOSA by a flexible connector, in order to align the optical source before affixing it permanently.

The invention discloses a plasma processing device which comprises an airtight reaction cavity. The reaction cavity comprises reaction cavity side walls and an insulating material window at the top, a base used for supporting a to-be-processed substrate is arranged in the reaction cavity, and a self-shielding inductance coil is fixed above the insulating material window. The plasma processing device is characterized in that the self-shielding inductance coil comprises a first coil, a middle coil and a third coil which are serially connected with one another, the middle coil is positioned below the first coil and the third coil, width of the middle coil is larger than that of the first coil or the third coil, a radio frequency power source applies a radio frequency electric field to space between an input end of the first coil and an output end of the third coil of the self-shielding inductance coil, the output end of the third coil is further connected with a balance adjusting circuit to enable standing waves on the self-shielding inductance coil, and voltage amplitude of the middle coil is smaller than that on the first coil or the third coil.