186results about How to "Reduce stray capacitance" patented technology

Systems and methods for generating a high voltage pulse. A series of voltage cells are connected such that charging capacitors can be charged in parallel and discharged in series. Each cell includes a main switch and a return switch. When the main switches are turned on, the capacitors in the cells are in series and discharge. When the main switches are turned off and the return switches are turned on, the capacitors charge in parallel. One or more of the cells can be inactive without preventing a pulse from being generated. The amplitude, duration, rise time, and fall time can be controlled with the voltage cells. Each voltage cell also includes a balance network to match the stray capacitance seen by each voltage cell.

A powered dispenser for dispensing individual sheet segments from a continuous roll of sheet material provided with spaced tear lines comprises a powered feed mechanism, a releasable, powered drive mechanism, a powered transfer mechanism, a pair of web sensing sensors, a capacitive sensing system providing automatic sensitivity adjustment, and control circuitry. A dual power supply system provides a mechanical lock-out functionality, and the control system is protected from electrostatic build-up on the surface of the feed roller. The web sensor, and an antenna plate of the capacitive sensing system, are provided on respective printed circuit boards mounted in overlying relation. Utilizing signals received from the pair of web sensors and the capacitive sensing system, the control circuitry senses the presence of a user to activate the powered drive mechanism, and prevents further dispensing of the sheet material until a previously dispensed segment is separated from the roll. The web sensors detection of a leading edge of the sheet material initiates a predetermined interval of sheet material advancement providing a proper placement of successive tear lines. Various approaches may be utilized to accommodate inadvertent sheet “tabbing” scenarios. The web sensors, together with the control circuitry, are also used to detect the depletion, or absence, of a working roll of sheet material, whereupon the control circuitry controls the powered transfer mechanism to automatically transfer the web feed supply from a depleted working roll to a reserve roll. The powered transfer mechanism may include a motor driven transfer bar, or provide motor driven release of a spring biased transfer bar. Another arrangement allows for ready release of a roll core, and drop of the same into an open dispenser cover for removal.

An electrostatic capacitance detection circuit 10 comprises an AC voltage generator 11, an operational amplifier 14 of which non-inverting input terminal is connected to specific potential (a ground in this example), an impedance converter 16, a resistance (R1) 12 connected between the AC voltage generator 11 and an inverting input terminal of the operational amplifier 14, a resistance (R2) 13 connected between the inverting input terminal of the operational amplifier 14 and an output terminal of the impedance converter 16, and an impedance element (a capacitor) 15 connected between an output terminal of the operational amplifier 14 and an input terminal of the impedance converter 16, and a capacitor to be detected 17 is connected between the input terminal of the impedance converter 16 and specific potential. The electrostatic capacitance detection circuit 10 and the capacitor 17 are located adjacently.

An antenna array may include an antenna element configured to receive an RF signal. A PIN diode may selectively couple the antenna element to an RF source. Biasing the PIN diode may cancel the received RF signal at a stub coupled to the diode thereby reducing stray capacitance of the PIN diode. A method for switching antenna elements is also disclosed. A PIN diode coupled to an antenna element is biased thereby reflecting the received RF signal out-of-phase within a stub such that the signal is canceling and stray capacitance of the PIN diode is reduced.

A coil component includes a first coil block and a second coil block that are sandwiched between magnetic substrates so as to form a chip body, and external electrodes that are attached to the chip body. The first coil block includes a coil body and an insulating body. The coil body includes an outer coil portion and an inner coil portion. The outer coil portion includes a first pattern group and a second pattern group, which are connected helically vertically in an alternating fashion. The inner coil portion includes a first spiral pattern and a second spiral pattern, which are connected to each other in series. In other words, low stray capacitance is achieved by the outer coil portion, while high inductance is achieved by the inner coil portion.

A capacitance tomography sensor is provided in the invention, wherein a sensor framework is added to the capacitance tomography sensor. A measurement electrode is arranged on an inner wall of the sensor framework to prevent direct contact between the measurement electrode and a to-be-test fluid. A shield electrode group is disposed on an outer side surface of the sensor framework to achieve electrical insulation from the measurement electrodes. By means of the structure, installation of the measurement electrode and the shield electrode group is more flexible.

A light-emitting device has a plurality of data lines and a plurality of pixel circuits. Each of the plurality of pixel circuits includes a light-emitting element that has a first electrode and a second electrode and that emits light having an intensity depending on the amount of driving current; a driving transistor that supplies the driving current to the first electrode; a holding transistor that supplies a driving signal supplied via the data lines to the driving transistor; and a connecting line that connects the driving transistor to the holding transistor. The second electrode is formed in a region different from a region in which the data lines are formed such that the second electrode is not opposite to some or all of the data lines.

A touch sensor panel is disclosed having an array of co-planar single-layer touch sensors fabricated on a single side of a substrate. The sense (or drive) lines can be fabricated in a single strip as columnar or zig-zag patterns in a first orientation, and the drive (or sense) lines can be fabricated as rows of polygonal (e.g. brick-shaped or pentagonal) conductive areas in a second orientation. Each sense (or drive) line in the first orientation can be coupled to a separate metal trace in the border area of the touch sensor panel, and each polygonal area in the second orientation can also be coupled to a metal trace in the border area of the touch sensor panel. The metal traces can allow both the row and column lines to be routed to the same edge of the substrate for flex circuit attachment.

Systems and methods for generating a high voltage pulse. A series of voltage cells are connected such that charging capacitors can be charged in parallel and discharged in series. Each cell includes a main switch and a return switch. When the main switches are turned on, the capacitors in the cells are in series and discharge. When the main switches are turned off and the return switches are turned on, the capacitors charge in parallel. One or more of the cells can be inactive without preventing a pulse from being generated. The amplitude, duration, rise time, and fall time can be controlled with the voltage cells. Each voltage cell may also includes a balance network to match the stray capacitance seen by each voltage cell. Droop compensation is also enabled.

Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.

A coil component includes a first coil block and a second coil block that are sandwiched between magnetic substrates so as to form a chip body, and external electrodes that are attached to the chip body. The first coil block includes a coil body and an insulating body. The coil body includes an outer coil portion and an inner coil portion. The outer coil portion includes a first pattern group and a second pattern group, which are connected helically vertically in an alternating fashion. The inner coil portion includes a first spiral pattern and a second spiral pattern, which are connected to each other in series. In other words, low stray capacitance is achieved by the outer coil portion, while high inductance is achieved by the inner coil portion.

Systems and methods for generating a high voltage pulse. A series of voltage cells are connected such that charging capacitors can be charged in parallel and discharged in series. Each cell includes a main switch and a return switch. When the main switches are turned on, the capacitors in the cells are in series and discharge. When the main switches are turned off and the return switches are turned on, the capacitors charge in parallel. One or more of the cells can be inactive without preventing a pulse from being generated. The amplitude, duration, rise time, and fall time can be controlled with the voltage cells. Each voltage cell may also include a balance network to match the stray capacitance seen by each voltage cell. Droop compensation is also enabled. Isolation diodes ensure that a discharge current can bypass inoperable voltage cells.

The invention discloses a pixel array of liquid crystal display devices, comprising M data lines, N scan lines and a plurality of pixel structures electrically connected with the data lines and the scan lines and arranged in an array, wherein each pixel structure comprises a switch component, at least one main pixel electrode, at least one pixel electrode, a first capacity coupling electrode pattern and a second coupling electrode pattern, the switch component is electrically connected with the first scan line and the first data line, at least one main pixel electrode and at least one pixel electrode are electrically connected with the switch component, the first and the second capacitor coupling electrode patterns are electrically connected with at least one main pixel electrode and are coupled with at least one pixel electrode in a capacitor type, the first capacitor coupling electrode pattern is adjacent to the first data line and the second capacitor coupling electrode pattern is adjacent to the second data line.