44results about How to "Minimum performance" patented technology

In a networking environment including one or more network processing (NP) devices and implementing a routing protocol for routing data packets from a source NP devices to destination NP devices via a switch fabric, with each network processing device supporting a number of interface ports, a system and method for enabling a routing system to recover more quickly that the routing protocol so as to significantly reduce the occurrence of lost data packets to a failed target interface / blade. The routing system is enabled to track the operational status of each network processor device and operational status of destination ports supported by each network processor device in the system, and maintains the operational status as a data structure at each network processing device. Prior to routing packets, an expedient logical determination is made as to the operational status of a target network processing device and target interface port of a current packet to be routed as represented in the data structure maintained at the source NP device. If the target blade / interface is not operations, an alternative route may be provided by ECMP. In this manner, correct routing of packets is ensured with reduced occurrence of lost data packets due to failed target NP devices / ports.

An integrated DWDM transmitter apparatus includes a silica-on-silicon substrate overlying a first support component. The silica-on-silicon substrate includes a silica layer overlying a silicon layer. A coefficient of thermal expansion of the first support component is substantially matched to a coefficient of thermal expansion of the silicon layer. An optical multiplexer is located within the silica layer and includes a plurality of input waveguides and at least an output waveguide. Additionally, the apparatus includes a second support component attached to a side surface of the first support component. One or more semiconductor laser array chips overlie the second support component. A coefficient of thermal expansion of the one or more semiconductor chips is substantially matched to a coefficient of thermal expansion of the second support component. Moreover, each of the one or more laser array chips includes one or more lasers, each of which is optically coupled to a corresponding one of the plurality of input waveguides.

The invention provides a colored golf ball comprising a core, a cover having a plurality of dimples formed on its surface, wherein the golf ball is two-piece structure consisting of a core and a cover, and the surface of the ball is coated with a coating comprising a pearlescent pigment. The ball satisfies the following conditions:(i) a color difference ΔE* between the core and the ball of at least 30;(ii) the core has a transparency which is up to 10% in terms of total transmittance and up to 1.0% in terms of parallel transmittance;(iii) the core has a lightness L* value, expressed in the L*a*b* color system based on JIS Z8729, of at least 82;(iv) the ball has a lightness L* value of at least 50;(v) the lightness L* value of the ball ≦the lightness L* value of the core;(vi) the cover has a thickness of from 0.1 to 2.1 mm,(vii) the cover has a transparency which is at least 50% in terms of total transmittance and at least 1.0% in terms of parallel transmittance; and(viii) the cover has a haze (H), mentioned in JIS K7105 (1981), of up to 98.The two-piece colored golf ball of the invention is a fluorescent ball which nonetheless retains a sense of transparency and has a high-quality feel, in addition to which it has a good weather resistance and is capable of preventing a change in color.

A lithium-ion rechargeable battery module having a plurality of lithium-ion battery cells, arranged that battery cells located at an high temperature portion of the module are electrically connected in parallel with battery cells located at a low temperature portion of the module. The battery cells at the high temperature portion have a higher electric resistance at 20° C. and a better high-temperature storage characteristic at 50° C. than those of the battery cells located at the low temperature portion.

A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process a sequence of operations including at least one memory access operation. The superscalar data processing apparatus comprises a plurality of execution pipelines for executing the operations, and issue logic for allocating each operation to one of the execution pipelines for execution by that execution pipeline. At least two of the execution pipelines are memory access capable pipelines which can execute memory access operations, and each memory access capable pipeline is associated with a subset of the plurality of execution threads. The issue logic is arranged, for each execution thread, to allocate any memory access operations of that execution thread to an associated memory access capable pipeline. Such a system has been found to provide an effective balance between increasing the efficiency of operation of the superscalar data processing apparatus when employing multiple execution threads whilst also alleviating the need for complex hardware to handle hazard detection.