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77results about How to "Improve data access speed" patented technology

Distributed caching method and system

The embodiment of the invention provides a distributed caching method and a distributed caching system, and relates to the field of data storage. The data access speed of the distributed caching system is increased. The method comprises the following steps that the distributed caching system acquires a data operation request of a service application, and performs hash operation according to a key value of data indicated to be operated by the data operation request to obtain the identification information of a virtual queue vBucket corresponding to the data; the distributed caching system acquires a corresponding relationship between the identification information of the vBucket and a caching service node, determines a first caching service node corresponding to the identification information of the vBucket according to the corresponding relationship, and allocates the data operation request to the first caching service node for corresponding data operation. The embodiment of the invention is used for distributed data caching.
Owner:LETV CLOUD COMPUTING CO LTD

Data access apparatus and data access method

A data access apparatus includes: a flash memory controller; a mirror means; and a flash memory including at least one data region and at least one mirror region. The mirror means copies data to form mirror data to the mirror region when the flash controller writes the data into the data region. The flash memory controller reads the mirror data to replace the data if the flash memory controller determines that the data include error(s) while the data are being read.
Owner:SILICON MOTION INC (TW)

Circuit and method for supplying page mode operation in semiconductor storing device

A semiconductor memory device having a partial activation framework, which provides an efficient page mode operation while operating in a partial activation mode. Control circuits and methods are provided to enable a page mode operation (for read and write data accesses) in a semiconductor memory device (such as a DRAM, FCRAM) having a partial activation framework, resulting in an improved data access speed when data is written / read from memory locations having the same wordline address. In one aspect, a method for accessing data in a memory device comprises activating a first wordline corresponding to a first address to perform a data access operation, receiving a second address after the first address, if the second address is the same as the first address, generating a page mode enable signal for maintaining an activated state of the first wordline corresponding to the first address while activating a second wordline corresponding to the second address, and deactivating the first and second wordlines in response to disabling of the page mode enable signal.
Owner:SAMSUNG ELECTRONICS CO LTD

Flash memory system

The invention relates to a flash memory storage system which comprises microcontroller, at least one flash memory of microcontroller with each flash memory including many entity storage blocks. Each entity storage block includes an entity address and many entity sectors which comprise at least one user data area and a logical address orienting fence, wherein each logical address orienting fence can write a logical address orienting data at user data area when it storage a entity data; logical address orienting data can log a corresponding logical address; a temporary storage which is connected with microcontroller can storage a connecting look-up table which can log each entity block's address and the corresponding logical address of logical storage block.
Owner:PROLIFIC TECH INC

Method for improving speed of storage system data access

The invention discloses a method for improving speed of storage system data access. The method for improving the speed of the storage system data access is capable of obtaining all the input output requests for low speed storage media, and redirecting the input output requests to high speed storage media according to an access situation. Therefore the aim of improving the speed of the storage system data access is achieved.
Owner:EISOO SOFTWARE

A distributed architecture data consistency method based on a Zookeeper

The invention discloses a distributed architecture data consistency method based on a Zookeeper, and relates to the technical field of data processing. The method comprises the following steps of: initializing buffer data: loading data in a Zookeeper into a memory of each node after each node of the distributed system is started; defining a subscription monitoring method, each node subscribes to aZookeeper directory and data, deploying monitoring; and data synchronization: after monitoring the data change in the Zookeeper, updating the memory data of each node through a deployed monitoring method, and keeping the data synchronization among the nodes. According to the invention, a Zookeeper component is used as a cache data synchronization manager in a distributed architecture system; thedistributed multi-node cache data is synchronized in real time by utilizing a release and subscription mechanism of the Zookeeper, and meanwhile, the data access speed is greatly increased based on aZookeeper database of a memory, so that the performance and the data consistency are well improved in a distributed architecture system.
Owner:科大国创云网科技有限公司

Fast speed computer system power-on & power-off method

A fast speed computer system power-on & power-off method, that is used to reduce an amount of main memory transferred and stored from a main memory into a second storage device, thus speeding up a speed of re-activation of a computer system from a hibernation state into a full speed operation state. Said fast speed computer system power-on & power-off method is applicable to various types of computer systems, and can be used to write in and load back data in cooperation with a random access processing technology. In addition, said method can be used to reduce extent of data loss and damage of said computer system due to a sudden power outage of said computer system.
Owner:NATIONAL CHUNG CHENG UNIV

Method for realizing follow-up safe access of user data

The invention discloses a method for realizing follow-up safe access of user data. A safe tunnel triggered by a user is realized to achieve safe transmission of non-inductive user data, then the isolation and safe access of the user data are accomplished by encryption technology irrelevant to a storage service provider, and the safe storage architecture method, which both has the speed and safety of private cloud and can provide the convenience of public cloud, can enable the user to truly experience the same safety and convenience of storing data on the cloud just like storing the data in local.
Owner:UNIV OF ELECTRONIC SCI & TECH OF CHINA

Synchronous control method of multithreading data acquisition system in acquisition times control mode

The invention relates to a synchronous control method of a multithreading data acquisition system in an acquisition times control mode, and belongs to the technical field of ground penetrating radars. The method comprises the steps that a times integer variable for controlling data acquisition is pre-established; a value after addition processing and a value after division processing of the times integer variable are subjected to Boolean operation together with two control variables respectively; results of the Boolean operation serve as synchronous control signals of different threads; synchronous control of multithreading in the mode is achieved by criterion functions of the threads and assignments of the control variables; and all the acquisition data can be stored by the preset criterion functions written in the threads. According to the method, a control function of the ground penetrating radar multithreading acquisition system is achieved on the basis of a computer control theory.
Owner:CHINA UNIV OF MINING & TECH (BEIJING)

Acceleration method for realizing inverse wavelet transform in JPEG2000 decompression algorithm by using GPU

The invention discloses an acceleration method for realizing inverse wavelet transform in an JPEG2000 decompression algorithm by using a GPU. The method comprises the following steps: firstly, performing optimized storage for inverse wavelet transform coefficients in a shard memory by using the advantage that the GPU shared memory is high in access speed; and secondly, adopting a parallel processing mode that one block processes a line (column) of pixels according to the characteristics that the line-line processing and column-column processing in the inverse wavelet transform process are independent of each other, adopting a parallel processing mode that one thread processes a plurality of pixels according to the characteristics that the processing of the same line (column) of pixels has dependence, but part of the processing procedure can still be parallel, and completing the inverse wavelet transform in a horizontal direction and a vertical direction. According to the inverse wavelet transform acceleration method disclosed by the invention, the advantages that the GPU has a large number of cores and is suitable for parallel computation are fully used, and the decompression speed of JEPG2000 can be improved effectively; and moreover, the algorithm structure is simple and reasonable, and is easy to implement on the GPU.
Owner:SHANDONG JIAOTONG UNIV

Memory management method, memory control circuit unit, and memory storage apparatus

A memory management method is provided according to an exemplary embodiment. The method includes: receiving a write command and determining whether a usage status of physical units associated to a storage area conforms to a first predetermined status; storing write data corresponding to the write command to at least one of physical units associated to a temporary area if the usage status of the physical units associated to the storage area conforms to the first predetermined status; associating the at least one physical unit storing the write data to the storage area; and allocating at least one logical unit to map the at least one physical unit associated to the storage area.
Owner:PHISON ELECTRONICS

Cache apparatus for increasing data accessing speed of storage device

A cache apparatus for increasing data accessing speed of a storage device includes: a non-volatile memory, for storing data; a memory controller, coupled to the non-volatile memory, for controlling data accessing operations of the non-volatile memory; a first transmission interface, coupled to the memory controller, for electrically connecting the memory controller to the storage device; and a second transmission interface, coupled to the memory controller, for electrically connecting the memory controller to a user-end personal computer.
Owner:JMICRON
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