153 results about "Scratch pad" patented technology

Update data to a non-volatile memory may be recorded in at least two interleaving streams such as either into an update block or a scratch pad block depending on a predetermined condition. The scratch pad block is used to buffered update data that are ultimately destined for the update block. Synchronization information about the order recording of updates among the streams is saved with at least one of the streams. This will allow the most recently written version of data that may exist on multiple memory blocks to be identified. In one embodiment, the synchronization information is saved in a first block and is a write pointer that points to the next recording location in a second block. In another embodiment, the synchronization information is a time stamp.

In a memory that is programmable page by page and each page having multiple sectors that are once-programmable, even if successive writes are sequential, the data recorded to an update block may be fragmented and non-sequential. Instead of recording update data to an update block, the data is being recorded in at least two interleaving streams. When a full page of data is available, it is recorded to the update block. Otherwise, it is temporarily recorded to the scratch pad block until a full page of data becomes available to be transferred to the update block. Preferably, a pipeline operation allows the recording to the update block to be set up as soon as the host write command indicates a full page could be written. If the actual write data is incomplete due to interruptions, the setup will be canceled and recording is made to the scratch pad block instead.

An authentication apparatus that makes it difficult to perform posing when accessing information is provided. When there is an access request from a mobile phone, an authentication server transmits a program to the mobile phone (S3202). The program is for reading data regarding an individual number (for example, serial number) recorded in a scratch pad of the mobile phone, and transmitting the data to the authentication server. The authentication server that receives the data regarding the serial number transmitted by activation of the program (S3202) compares the serial number with data regarding the identification number of each mobile phone, the data being maintained in the authentication server (S3203). When the serial number matches any of serial numbers maintained therein (S3203: Yes), the authentication server authenticates the access to be valid.

Disclosed herein, among other things, are methods and apparatus for hearing assistance devices, including, but not limited to connections for receiver-in-canal hearing devices. In various embodiments, a hearing device includes a hearing device component adapted to rest on or behind the ear and hearing assistance electronics disposed in the component. A first connector portion is disposed in the component, the first connector portion electrically connected to the hearing assistance electronics. A second connector portion is adapted to conform to a portion of the component and to electrically and physically connect a cable to the first connector portion. In various embodiments, at least one of the first connector portion and the second connector portion employ scratch pads for contacts. The first connector portion is top loading, in an embodiment.

An address containing data to be accessed is determined in response to executing an instruction received at a processor core of a microprocessor. During a scratch-pad mode of operation, it is determined whether a set of cache lines of a data cache is accessible based upon the memory location from which the instruction was retrieved. The address space of the data cache during scratch-pad mode can be isolated from other address spaces.

A multiprocessor system includes a main memory and multiple processing cores that are configured to execute software that uses data stored in the main memory. In some embodiments, the multiprocessor system includes a data streaming unit, which is connected between the processing cores and the main memory and is configured to pre-fetch the data from the main memory for use by the multiple processing cores. In some embodiments, the multiprocessor system includes a scratch-pad processing unit, which is connected to the processing cores and is configured to execute, on behalf of the multiple processing cores, a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data.

Software Managed Manycore (SMM) architectures with scratch pad memory for reach core are a promising solution for scaling memory. In these architectures the code and data of the tasks mapped to the cores is explicitly managed by the compiler and often require inter-procedural information and analysis. But, a call graph of the program does not have enough information, and the Global CFG has too much information. Most new techniques informally define and use GCCFG (Global Call Control Flow Graph)—a whole program representation that succinctly captures the control-flow and function call information—to perform inter-procedural analysis. Constructing GCCFGs for several cases in common applications. The present disclosure provides unique graph transformations to formally and correctly construct GCCFGs for optimal compiler management of manycore systems.

The invention relates to a dynamic imaging method for multilayer flatten layers and a system thereof, wherein, the imaging system is mainly provided with a graphic engine, a special effect procedure, a plurality of layer storage areas and a scratch pad area for layer attributes in an external memory; first a special effect procedure is carried out before leading a user interface to assume a dynamic imaging method, then three types of image layers corresponding to a background picture, a functional picture and a special effect picture which are on the user interface are obtained, afterward imaging attribute values to which the image layers belong are defined for the following merged describing for a plurality of image layers; namely, the sequence of all the image layers is determined by the imaging depth value of each image layer, the merged describing of all the image layers is carried out according to the sequence; therefore, a plurality of functional patterns of the functional picture can be integrated into the user background and the special effect picture and present an unanticipated gorgeous user interface picture.

Hypervisors are a new technology in the industry that enable multiple Operating Systems to co-exist on a single client. The use of a hypervisor provides a novel approach to email virus protection. The hypervisor is able to fire up an Operating System on demand, for a specific purpose, or have it running from the powering of the computer. A second Operating System can be provided as a donor Operating System that acts as a scratch area or scratch pad. Emails sent to the recipient are opened under the donor Operating System, or the “Scratch OS”. Once the email activities are complete, the “Scratch OS” can be discarded. Thus, any damage that may be caused by an email virus would be nil, and further the User Operating System would be undamaged. This method would be effective in precluding any damage that a virus may have done.

A garbage collector that employs the train algorithm to manage a generation in a computer system's dynamically allocated heap maintains for each of the generation's cars a respective remembered set that identifies all locations where references to objects in that car have been found by scanning locations identified by the mutator as having been modified. To avoid some of the expense of remembered-set updating, the collector refrains from attempting to add to a remembered set any reference located in a car that will be collected during the next collection increment. Additionally, if no mutator operation will occur before a collection set of one or more cars will be collected, any reference located outside that collection set but referring to an object within the collection set is not recorded in a remembered set but is recorded instead in a scratch-pad list of entries that identify references to collection-set objects that need to be evacuated.

The invention discloses a heterogeneous multi-core microprocessor based on a multilayer bus. The heterogeneous multi-core microprocessor comprises a plurality of processing cores for uniform addressing, wherein the plurality of processing cores have different pipeline structures; the plurality of processing cores are connected through an AXI bus with bridge connection; the AXI bus with bridge connection is connected with a notepaper type memory; data packets are sent and read between every two processing cores through a scratch pad memory; a data packet head address and a data packet length are directly sent between every two processing cores so as to assist in completing the transmission of a data packet between the two processing cores; and the AXI bus with bridging is also connected with a peripheral interface, and the processing cores perform access control on external equipment through the peripheral interface. According to the heterogeneous multi-core microprocessor based on themulti-layer bus, disclosed by the invention, the communication delay can be reduced.

The present invention provides processing systems, apparatuses, and methods that access a scratch pad on-demand to reduce power consumption. In an embodiment, an instruction fetch unit initiates an instruction fetch. When a scratch pad is enabled, an instruction is retrieved from the scratch pad in parallel with a translation of a virtual address to a physical address. If the physical address is associated with the scratch pad, the retrieved instruction is provided to an execution unit. Otherwise, the scratch pad is disabled to reduce power consumption and the instruction fetch is re-initiated. When the scratch pad is disabled, an instruction is retrieved from another instruction source, such as an instruction cache, in parallel with the translation of the virtual address to the physical address. If the physical address is associated with the scratch pad, the scratch pad is enabled and the instruction fetch is re-initiated.

The invention discloses a method for dynamically allocating on-chip heterogeneous memory resources by utilizing a virtual memory mechanism, comprising the following steps of: analyzing the time and space distribution of data sections (comprising global data, stack data, pile data and constant pool data) with data Cache conflicts caused by high frequency by adopting a time slot analyzing method, then obtaining the time slot conflict diagram of the data Cache by the distribution and carrying out mathematical abstraction for the time slot conflict diagram. According to the target function of energy consumption and the target function of performance, a program part to be optimized is selected by using an integer nonlinear programming method and then is dynamically remapped in an on-chip data SPM (Scratch-pad Memory) by utilizing clock interrupt, and thereby, the extra memory access caused by the data Cache conflicts can be avoided. The method can reduce the energy consumption of a system and enhance the performance of the system due to the full utilization of on-chip heterogeneous memory.

The invention discloses an on-chip scratch-pad memory (SPM) management method facing a multitasking embedded system. The on-chip scratch-pad memory management method comprises the steps as follows: pre-analyzing a program code segment; tracking a program to obtain an internal storage instruction accessing sequence of the program, so as to acquire the accessing times of an internal storage code block and Cache miss information, and accounting and recording a space-time conflict set of the internal storage code block under access of the Cache; selecting an algorithm as required to obtain an optimized SPM distribution scheme; generating a code distribution dispersion loading file, newly mapping and distributing the program code segment, and newly compiling codes to obtain an optimal execution result. Via comprehensive consideration of accessing frequency, cache miss frequency, intertask and intra-task conflict, the required optimal distribution is obtained, the utilization rate of the SPM is maximized, and finally under the premise of ensuring the real-time performance of the program, an optimal execution time scheme or an optimal energy conservation scheme is obtained.

Modular pet furniture providing a place for pets, in particular, cats, to rest, sleep and recreate, comprising a frame structure, a bed structure, a pet support and an attachment mechanism. The frame structure forms a single or a plurality of support regions or compartments that can accommodate different bed styles and different numbers of pets. The support regions also provide space for toys and other items of interest for pets, such as scratch pads. The modular pet furniture can be configured to contain a variable number of support regions in a number of different stacking configurations, to form pet furniture of a variety of shape and size.