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163results about How to "Fine pitch" patented technology

Semiconductor package with embedded die

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.
Owner:STATS CHIPPAC INC

Microelectronic assemblies having very fine pitch stacking

A microelectronic assembly includes two or more microelectronic packages stacked at a fine pitch, which is finer than the pitch that is possible when using solder balls for making the joint. Each stackable package desirably includes a substrate having pins projecting from one surface of the substrate and solder balls projecting from the other surface of the substrate. Each stackable package may have one or more die attached to one or more of the surfaces of the substrate. In certain embodiments, die may be attached to both surfaces of the substrate. The dies may be electrically interconnected with the substrate using wire bonds, flip chip bonding, leads and/or stud bumping. The die may be encapsulated in an encapsulated material, under-filled or glob topped. In certain preferred embodiments, the combination of the conductive post height and ball height is equal to or greater than the height of the encapsulated or molded chip structure. The combination of the conductive post height and the ball height must be at least equal to the height of the encapsulated chip structure so that the conductive elements are able to span the gap between layers of the assembly. After the tips of the conductive pads are in contact with the solder masses, the solder masses are reflowed to form a permanent electrical interconnection between the stacked microelectronic packages. During reflow, the reflowed solder will wick up around the conductive posts to form elongated solder columns. In addition, when the solder is reflowed, surface tension pulls the opposing layers of the assembly toward one another and provides a self-centering action for the conductive posts.
Owner:TESSERA INC

High strength and high toughness heavy haul train wheel steel and heat treatment method thereof

ActiveCN106521315AReduce the amount of processingExcellent match between toughness and plasticityFurnace typesHeat treatment furnacesRoom temperatureQuenching
Belonging to the technical field of steel for railway wheels, the invention relates to a high strength and high toughness heavy haul train wheel steel and a heat treatment method thereof. The steel comprises the following chemical components by weight percentage (wt.%): 0.75-0.85wt.% of C, 0.80-1.00wt.% of Si, 0.40-0.80wt.% of Cr, 0.30-0.50wt.% of Mn, 0.01-0.03wt.% of Nb, 0.02-0.06wt.% of V, 0.010-0.025wt.% of Al, less than 0.015wt.% of P, less than 0.015wt.% of S, and the balance Fe and unavoidable impurities. After conventional smelting, casting and forging, a wheel is subjected to a novel heat treatment process adopting tread quenching and sub-sectional cooling. After heat treatment, the structure at a standard tensile test position of a rim is a fully lamellar perlite structure, the size of a pearlite colony is 2-6microm, and the pearlite interlamellar spacing is 0.05-0.09microm. The room temperature tensile strength of the rim is 1200MPa grade, the percentage elongation after fracture is greater than 12%, and the web 20DEG C impact energy KU2 is greater than 20J. Therefore, the high strength and high toughness heavy haul train wheel steel has excellent strength and toughness matching, and can be used for heavy haul trains.
Owner:CENT IRON & STEEL RES INST +1

Fabrication method of space transformer for semiconductor test probe card

The invention discloses a space transformer for a semiconductor test probe card and a method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than, the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads. In some embodiments, the test pads may be C4 test pads. The invention shortens the spacedistribution of the contact test pads.
Owner:TAIWAN SEMICON MFG CO LTD
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