37 results about "Jazelle" patented technology

An apparatus includes a processor to generate a random exponent having a fixed bit width, divide the random exponent into a pre-exponent portion and a post-exponent portion at a random bit position in the fixed bit width, and generate a cryptographic key using the pre-exponent portion and the post exponent portion

The invention discloses a matrix multiplication acceleration method oriented to a heterogeneous fusion system structure, and aims to design a universal matrix multiplication acceleration method oriented to the heterogeneous fusion system structure for different many-core accelerator target system structures and improve the use efficiency of a heterogeneous system. According to the technical scheme, firstly, block matrix multiplied versions facing a heterogeneous fusion system structure are designed, the block matrix multiplied versions comprise vcpu, vgpu, vmic, vscif, vcoi and vtarget, and then the heterogeneous fusion multi-version matrix multiplied versions are integrated and packaged to generate a library file HU-xgemm of the heterogeneous fusion version; finally, an accelerator in anHU-xgemm adaptive heterogeneous fusion system structure is adopted. According to the invention, different target accelerators and processors can be self-adapted; matrix multiplication can be adaptively carried out according to different heterogeneous fusion system structures, matrix multiplication is carried out according to topological structures of CPUs or accelerators in the different heterogeneous fusion system structures, FMA parallel computing is carried out, the matrix multiplication speed is increased, and the use efficiency of a heterogeneous system is improved.

The present invention provides a heterogeneous acceleration system and method based on a CTPN network, including a CPU end and an FPGA end; the FPGA end includes a first sub-graph and a second sub-graph, and the CPU end includes a third sub-graph; The first sub-graph includes the CTPN network CNN part, the second sub-graph includes the RNN part, and the third sub-graph includes the rest of the CTPN network; the first sub-graph and the second sub-graph are executed on the FPGA side, and the second sub-graph is executed on the FPGA side. The three subgraphs are executed on the CPU side; the output of the FPGA side is used as the input of the third subgraph; the CPU side finally implements network inference and obtains the final result. The present invention can greatly increase the inference speed of the CTPN network with little decrease in precision, and enables the accelerator to better realize the function of real-time scene character recognition.

Exploiting FPGAs for acceleration may be performed by transforming concurrent programs. One example mode of operation may provide one or more of creating synchronous hardware accelerators from concurrent asynchronous programs at software level, by obtaining input as software instructions describing concurrent behavior via a model of communicating sequential processes (CSP) of message exchange between concurrent processes performed via channels, mapping, on a computing device, each of the concurrent processes to synchronous dataflow primitives, comprising at least one of join, fork, merge, steer, variable, and arbiter, producing a clocked digital logic description for upload to one or more field programmable gate array (FPGA) devices, performing primitive remapping of the output design for throughput, clock rate and resource usage via retiming, and creating an annotated graph of the input software description for debugging of concurrent code for the field FPGA devices.

The invention provides an SNOW-V algorithm accelerator applied to a 5G system and an acceleration method of the SNOW-V algorithm accelerator. The accelerator comprises an LFSR module which is composed of two shifting registers and a circulation structure and used for generating data needed by SNOW-V algorithm operation. The accelerator further comprises an FSM module composed of a register, an adder and an AES encryption wheel; a key stream is finally generated and continuously output through cyclic calculation among units in the FSM module, and a ciphertext is obtained after the key stream and a plaintext are subjected to XOR. The hardware architecture provided by the invention is high in resource utilization rate, and the key stream can be quickly generated; meanwhile, the ultra-high-speed encryption requirement of a 5G system can be met in the future.