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Audio noise reduction accelerator system and method based on RISC v custom instruction set expansion

An audio noise reduction, custom technology, applied in the direction of instruments, sounding equipment, etc., can solve the problem of lack of flexibility, and achieve the effect of reducing hardware resources, reducing the number of instructions, and reducing the number of execution cycles

Pending Publication Date: 2021-12-28
CHONGQING UNIV OF POSTS & TELECOMM
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AI Technical Summary

Problems solved by technology

Such a method is often inflexible, and retraining is required for different noise sources. At the same time, such a method does not have the flexibility to adopt software and hardware co-processing. Therefore, the present invention is based on the audio noise reduction of RISCv custom instruction set expansion Accelerator system will provide a new approach to audio noise reduction

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  • Audio noise reduction accelerator system and method based on RISC v custom instruction set expansion

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Embodiment Construction

[0045] The technical solutions in the embodiments of the present invention will be described clearly and in detail below with reference to the drawings in the embodiments of the present invention. The described embodiments are only some of the embodiments of the invention.

[0046] The technical scheme that the present invention solves the problems of the technologies described above is:

[0047] A kind of audio noise reduction accelerator system based on RISC v self-defined instruction set expansion designed by the present invention, as attached figure 1 As shown, its structure includes: E203_CORE, NICE_CORE, NICE_Interface, E203_SOC, audio codec WM8731 module, audio noise reduction FxLMS algorithm; where:

[0048] Described E203_SOC is made up of E203_CORE, NICE_CORE, ICB_APB, UART serial port, IIC interface and IIS interface; Wherein, save the executable file that produces after compiling and assembling link of C language program through off-chip Flash memory, after system...

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Abstract

The invention discloses an audio noise reduction accelerator system and method based on RISC v custom instruction set expansion, and belongs to the technical field of integrated circuits. The system mainly comprises an E203_CORE, an NICE_CORE, a NICE_Interface, an E203_SOC, an audio coding and decoding WM8731 module, and an audio noise reduction FxLMS algorithm, wherein the E203_CORE is connected with the NICE_CORE through the NICE_Interface, the E203_CORE, the NICE_CORE and a related peripheral port form the E203_SOC together, the E203_SOC is connected with the audio coding and decoding WM8731 module, and the audio noise reduction FxLMS algorithm is downloaded into a core of the RISC v processor through software programming to run. Compared with a processor of an ARM instruction set architecture, the processor adopting an RISC v custom instruction set can accelerate a specific operation part in the audio noise reduction FxLMS algorithm; and the problems of area, power consumption, granularity and the like can be better optimized, and the flexibility and feasibility of the algorithm are improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an audio noise reduction accelerator system and method based on RISC V self-defined instruction set expansion. Background technique [0002] With the development of the economy and the continuous advancement of technology, there are more and more application scenarios for audio noise reduction systems, such as noise reduction in cars, noise reduction in gas stations, and earphone noise reduction. However, at present, passive noise reduction methods such as physically isolating noise sources are often adopted. The method of using active noise reduction to allow sound source signals to superimpose and cancel is often difficult to implement in hardware. It is difficult to use FPGA for hardware implementation of improved excellent algorithms. Therefore, it is adopted The software implementation will enable the improved algorithm to be realized, which will be a...

Claims

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Application Information

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IPC IPC(8): G10K11/178
CPCG10K11/17881G10K11/17853
Inventor 袁军赵强孟祥胜李军
Owner CHONGQING UNIV OF POSTS & TELECOMM
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