Tensor processor instruction set architecture

Abstract

A hardware accelerator having an efficient instruction set is disclosed. An apparatus may comprise logic configured to access a first and a second machine instruction. The second machine instruction may be missing a tensor operand needed to execute the second machine instruction. The logic may be further configured to execute the first machine instruction, resulting in a tensor. The logic may be further configured to execute the second machine instruction using the resultant tensor as the missing tensor operand.

Description

Background technique [0001] Computing increasingly requires extremely powerful processors. For example, machine learning, such as but not limited to deep neural networks, requires processors capable of performing an extremely high number of operations per second. Performing machine learning, such as but not limited to deep neural networks, on a general-purpose central processing unit (CPU) can be prohibitively expensive. [0002] Hardware accelerators have been used to supplement processing performed on general-purpose CPUs. Contents of the invention [0003] Certain embodiments described herein relate to a hardware accelerator with an efficient instruction set. In one embodiment, an apparatus includes logic configured to access a first machine instruction and a second machine instruction in a set of machine instructions. The second machine instruction is missing a tensor operand required to execute the second machine instruction. The logic is also configured to execute ...

AI Technical Summary

Problems solved by technology

Performing machine learning (such as but not limited to deep neural networks) on a general-purpose central processing unit (CPU) can be prohibitively expensive

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