96 results about "Dram capacitor" patented technology

A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

A high capacitance embedded metal interconnect capacitor and associated fabrication processes are disclosed for using a directional barrier metal formation sequence in a dual damascene copper process to form multi-layer stacked copper interconnect structure having reduced barrier metal layer formation at the bottom of each via hole so that the multi-layer stacked copper interconnect structure may be readily removed and replaced with high capacitance MIM capacitor layers.

A method of forming a trench capacitor comprises steps of forming a trench in a substrate, partially filling the trench with a first conductive material, lining a portion of the trench above the first conductive material with a collar material, etching the collar material to a strap depth below a top of the trench, and filling the trench with a second conductive material, wherein a portion of the second conductive material positioned between the strap depth and the top of the trench comprises a buried strap.

A method of patterning a metal surface by electro-mechanical polishing is disclosed. A metal surface is placed in fluid communication with an abrasive surface of a pad. The two surfaces are moved relative to each other, in acidic fluid which contains abrasive particles. An electrical circuit is formed between the metal surface and abrasive pad and a current is supplied to the circuit. The patterned surface then is processed into a useful feature such as a bottom electrode for a DRAM capacitor.

An array of DRAM cells having Y-shaped multi-fin stacked capacitors with increased capacitance is achieved. A planar first insulating layer is formed over the semi-conductor devices on the substrate. Polycide bit lines are formed on the first insulating layer, and a second insulating layer and a silicon nitride (Si3N4) etch-stop layer are conformally deposited. A multilayer, composed of a alternating insulating and polysilicon layers, is conformally deposited over the bit lines. Capacitor node contact openings are etched in the multilayer and in the underlying layers to the substrate. A fourth polysilicon layer is deposited sufficiently thick to fill the node contact openings and to form the node contacts. The multilayer is then patterned to leave portions over the node contacts, and an isotropic etch is used to remove the insulating layers exposed in the sidewalls of the patterned multilayer to provide Y-shaped multi-fin capacitor bottom electrodes over the bit lines. These Y-shaped multi-fin capacitors increase the capacitance by 37% over T-shaped multi-fin capacitors. The DRAM capacitors are then completed by forming an interelectrode dielectric layer on the bottom electrodes and by depositing a fifth polysilicon layer to form the capacitor top electrodes.

A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal compound and the conductive binary metal compound is annealed in a reducing atmosphere to promote the formation of a desired crystal structure. The binary metal compound may be a metal oxide. Annealing the metal oxide (i.e. molybdenum oxide) in a reducing atmosphere may result in the formation of a first electrode material (i.e. MoO₂) with a rutile-phase crystal structure. This facilitates the formation of the rutile-phase crystal structure when TiO₂ is used as the dielectric layer. The rutile-phase of TiO₂ has a higher k value than the other possible crystal structures of TiO₂ resulting in improved performance of the DRAM capacitor.

A memory device that is comprised of a dynamic random access memory (DRAM) capacitor and a nitride read only memory (NROM) transistor. The memory device provides multiple modes of operation including a DRAM mode using the capacitor and a non-volatile random access memory mode using the NROM transistor. The device is comprised of two source/drain regions between which a gate insulator layer is formed. A control gate, coupled to a word line, is formed on top of the gate insulator. The DRAM capacitor is coupled to one of the source/drain regions while the second source/drain region is coupled to a bit line that is eventually coupled to a sense amplifier for reading the state or states of the memory device.

A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 μΩcm. Advantageously, the electrode materials are conductive molybdenum oxide.

A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a doped material formed from a first dopant in concert with a second dopant wherein the second dopant has a different physical size from the first dopant and the presence of the second dopant influences the solubility of the first dopant in the dielectric material. The dielectric material maintains a high k-value while minimizing the leakage current and the EOT value

The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and depositing a layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. A thin layer of amorphous silicon is then formed over the HSG-Si layer. This textured polysilicon structure forms the lower electrode of the DRAM capacitor. A dielectric layer is formed on the lower electrode, and an upper electrode is formed from a second layer of doped polysilicon. As-formed HSG-Si grains tend to form sharp intersections with the polysilicon layers on which they grow. When these HSG-Si grains are exposed to a thermal oxidation environment, poor quality oxides are formed at the sharp corners between the HSG-Si grains and the doped polysilicon layer. The poor quality oxides at the sharp corners between the HSG-Si grains and the doped polysilicon layer break down comparatively readily, and appears to cause leakage currents in capacitors having HSG-Si electrodes. By growing a thin amorphous silicon layer over the surface of the HSG-Si layer, the intersection between the HSG-Si grains and the layer of polysilicon is rounded. Subsequent growth of a thermal oxide, or the formation of other dielectric layers, provides a more reliable capacitor.

The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-SI on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.