Method for manufacturing DRAM capacitor structure and formed structure

Abstract

The invention relates to a method for forming a capacitor structure used for a dynamic random access memory. The method comprises the steps as follows: a cover semiconductor substrate is formed; a first dielectric layer of a cover device is formed; a via hole in the first dielectric layer is formed; a first oxide layer covering the first dielectric layer is formed; a barrier layer covering the first oxide layer is formed; a second oxide layer covering the barrier layer is formed; a groove region which passes through a part of the second oxide layer, a part of the barrier layer and a part of the first oxide layer is formed; a bottom electrode structure is formed to sketch out the groove region; a mask layer is used for protecting the bottom electrode structure and selectively removing the second oxide layer and up to the barrier layer which has etching and resisting effect to expose the external region of the bottom electrode structure; dielectric layers of the capacitor which cover the external region of the bottom electrode structure and the internal region of the bottom electrode structure are formed; a plate of the upper capacitor which covers the dielectric layers of the capacitor is formed to form the capacitor structure.

Description

technical field [0001] The present invention relates to integrated circuits and their processing for use in the manufacture of semiconductor devices. In particular, the present invention provides methods and structures for fabricating capacitor structures for dynamic random access memory, commonly referred to as DRAM. It should be recognized, however, that the scope of the invention is much broader. Background technique [0002] Integrated circuits have grown from a few to millions of interconnected devices fabricated on a single silicon wafer. Traditional integrated circuits have provided performance and complexity far beyond what was originally imagined. In order to increase complexity and circuit density (i.e., the number of devices that can be packaged on a given chip area), the minimum device feature size, also known as device "geometry (geometry)", has increased with the size of integrated circuits. Development becomes smaller. [0003] Increasing circuit density n...

AI Technical Summary

Problems solved by technology

Although significant improvements have been made, this design still has many limitations

Just as an example, these designs must get smaller and smaller but still need to store large capacitance values

Additionally, these capacitor designs tend to be difficult to manufacture and often require complex fabrication processes and structures, which results in inefficiencies and possibly low yields due to leakage

Images