The invention relates to the technical field of chip verification, in particular to an SOC verification system and method based on UVM, and the system comprises a test excitation which covers design specifications and is randomly generated, a verification environment layer which is formed by combining a plurality of IP_ENVs, and a system-on-chip SOC based on a risc-v kernel. Each IP_ENV comprises a scoreboard, a kernel register, a reference model, an excitation generator, a driver and a monitoring module. When data sent by peripheral equipment to the SOC is verified, a verification environment is directly multiplexed to generate and send an excitation signal, and the scoreboard accesses the kernel register through a back door and automatically compares the kernel register with an expected value of the reference model to obtain a verification result; when the data sent to a bus by the SOC is verified, the excitation generator and the driver are closed, a driving program is loaded to the risc-v kernel, an IP module is driven by the on-chip bus to send the data, the monitoring module collects the sent data, and the scoreboard judges a final result. The system has the following beneficial effects that the verification time is greatly shortened while the test flexibility is ensured.