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87results about How to "Reduce threading dislocation density" patented technology

Method for Producing Virtual Ge Substrates for III/V-Integration on Si(001)

Relaxed germanium buffer layers can be grown economically on misoriented silicon wafers by low-energy plasma-enhanced chemical vapor deposition, in conjunction with thermal annealing and / or patterning, the buffer layers can serve as high-quality virtual substrates for the growth of crack-free GaAs layers suitable for high-efficiency solar cells, lasers and field effect transistors.
Owner:DICHROIC CELL

Sapphire substrate, epitaxial substrate and semiconductor device

An epitaxial substrate for manufacturing field effect transistor (FET) that has heterojunction structure consisting of at least a channel layer made of gallium nitride or gallium indium nitride and a barrier layer made of aluminum gallium nitride formed successively on the principal plane of the sapphire substrate, wherein the principal plane of the sapphire substrate semiconductor is inclined from (01-12) plane toward (0001) plane by an off-angle α that is in a range of 0°<x≦5°. With this constitution, an epitaxial substrate for manufacturing field effect transistor having high smoothness is provided.
Owner:KYOCERA CORP

Semiconductor substrate, field-effect transistor, and their production methods

A semiconductor substrate manufacturing method has a first layer formation process, a second layer formation process, a heat treatment process, and a polishing process; in the first layer formation process, the thickness of the first SiGe layer is set to less than twice the critical thickness, which is the film thickness at which dislocations appear and lattice relaxation occurs due to increasing film thickness; in the second layer formation process, the Ge composition ratio of the second SiGe layer is at least at the contact face with the first SiGe layer or with the Si layer, set lower than the maximum value of the Ge composition ratio in the first SiGe layer, and moreover, a gradient composition region in at least a portion of which the Ge composition ratio increases gradually toward the surface is formed. By this means, the penetrating dislocation density is kept low, surface roughness is low, and worsening of roughness at the surface and at interfaces due to heat treatment in device manufacturing processes or similar is prevented.
Owner:SUMCO CORP

Method and system for lattice space engineering

A system for manufacturing multilayered substrates. The system has a support member is adapted to process a film of material comprising a first side and a second side from a first state to a second state. The support member is attached to the first side of the film of material. The second state comprises a stressed state. The system has a handle substrate comprising a face, which is adapted to be attached to the second side of the film of material. The support member is capable of being detached from the first side of the film of material thereby leaving the handle substrate comprising the film of material in the second state being attached to the face of the handle substrate.
Owner:SILICON GENERAL CORPORATION

Method of reducing dislocation-induced leakage in a strained-layer field-effect transistor

A structure and method of fabricating a semiconductor field-effect transistor (MOSFET) such as a strained Si n-MOSFET where dislocation or crystal defects spanning from source to drain is partially occupied by heavy p-type dopants. Preferably, the strained-layer n-MOSFET includes a Si, SiGe or SiGeC multi-layer structure having, in the region between source and drain, impurity atoms that preferentially occupy the dislocation sites so as to prevent shorting of source and drain via dopant diffusion along the dislocation. Advantageously, devices formed as a result of the invention are immune to dislocation-related failures, and therefore are more robust to processing and material variations. The invention thus relaxes the requirement for reducing the threading dislocation density in SiGe buffers, since the devices will be operable despite the presence of a finite number of dislocations.
Owner:ALSEPHINA INNOVATIONS INC

Macrolattice mismatch epitaxial buffer layer structure containing digital dislocation separating layers and preparation method thereof

InactiveCN102254954AReduce threading dislocation densityImproved lattice quality and optoelectronic propertiesFinal product manufactureSemiconductor devicesDislocationBeam source
The invention relates to a macrolattice mismatch epitaxial buffer layer structure containing digital dislocation separating layers and a preparation method thereof. The structure is characterized in that n layers of digital alloy dislocation separating layer materials are inserted into an ingredient gradual changing buffer layer. The preparation method comprise the following steps: adjusting beam source temperature, growing a ingredient gradual changing buffer layer on a substrate, and according to present gradual changing ingredient, forming a digital alloy dislocation separating layer through growing short period superlattice; adjusting the beam source temperature again, growing a ingredient gradual changing buffer layer, regrowing a digital alloy dislocation separating layer according to present gradual changing ingredient; regrowing a ingredient gradual changing buffer layer in above sequence until the buffer layer ingredient gradually changes to a desirable value to obtain the macrolattice mismatch epitaxial buffer layer structure. According to the invention, the macrolattice mismatch epitaxial material takes place relaxation and releases stress rapidly and effectively in the buffer layer and isolates penetrating dislocation, thus penetrating dislocation density of the epitaxial material on the buffer layer is reduced, and crystal lattice quality and photoelectric characteristic of the macrolattice mismatch epitaxial material on the buffer layer are improved.
Owner:SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI

Semiconductor wafer comprising gallium nitride layer having one or more silicon nitride interlayer therein

A semiconductor wafer comprising a substrate layer and a first GaN layer having one or more SiNx interlayers therein, wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10 nm.
Owner:INTELLEC

Method for Producing Group III Nitride Semiconductor and Group III Nitride Semiconductor

A first side surface of post of the first stripe is formed so that a plane which is most parallel to the first side surface among low-index planes of the growing Group III nitride semiconductor is a m-plane (10-10), and a first angle between the first lateral vector obtained by orthogonally projecting a normal vector of the first side surfaces to the main surface and a m-axis projected vector obtained by orthogonally projecting a normal vector of the m-plane of the growing semiconductor to the main surface is from 0.5° to 6°. A second side surface of post of the second stripe is formed so that a plane which is most parallel to the second side surface among low-index planes of the growing semiconductor is an a-plane (11-20), and a second angle between the second lateral vector and an a-axis projected vector of the a-plane is from 0° to 10°.
Owner:TOYODA GOSEI CO LTD

Device and method for preparing high-quality large-diameter SiC single crystal

The invention discloses a device and a method for preparing a high-quality large-diameter SiC single crystal, which belong to the field of SiC crystal growth, the device comprises a crucible, a thermal insulation layer, a heating device and a porous graphite barrel; wherein the crucible is positioned in the thermal insulation layer; the heating device is located on the outer side of the thermal insulation layer; the seed crystal and a porous graphite barrel are positioned in the crucible and are coaxial with the crucible; according to the invention, a transportation mode of the SiC growth components is from raw materials on the outer side of the crucible to seed crystals on the inner side of the crucible, the crystal growth process is a natural expanding process, expanding of the diameterof the crystal is not limited, meanwhile, the crystal grows along a non-polar growth face, and the penetration dislocation density is greatly reduced compared with that of the crystal growing along aC axis; C particles generated by the SiC raw material which is heated and carbonized next to the crucible wall are effectively blocked by the SiC raw material on the inner side and the porous graphitelayer, so that C inclusions in the crystal are reduced, and the quality of the crystal is effectively improved.
Owner:河北同光科技发展有限公司

Seed crystal support and method for reducing penetration type dislocation density in silicon carbide single crystal

The invention provides a seed crystal support and a method for reducing penetration type dislocation density in a silicon carbide single crystal. The grooves are formed in the seed crystal support, the grooves are filled with the materials with the heat conductivity different from that of graphite, or the seed crystal support is directly plated with the thin film with the heat conductivity different from that of the graphite, so that two substances with the different heat conductivities exist on the surface of the seed crystal support during crystal growth, heat dissipation is uneven, and thenuneven distribution of a temperature field on the surface of the seed crystal is caused. Therefore, periodic distribution of two substances with different thermal conductivities on the seed crystal support can be utilized; according to the method, the distribution of a seed crystal surface temperature field in the SiC physical vapor transport growth process is modulated, preferential nucleation is forced to be carried out in a low-temperature area corresponding to a predefined pattern, selective preferential growth is carried out according to the predefined pattern, and then lateral growth iscarried out, so that the purpose of reducing the penetration type dislocation density is achieved.
Owner:广州南砂晶圆半导体技术有限公司
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