The invention relates to an
embedded system power on self test method. The method comprises the following steps: (1), electrifying a
system, and detecting a center
processing unit (CPU) register; (2), detecting
internal memory by a cross blocking method being used, and judging whether breakdowns exist in the
internal memory or not; (3), classifying instructions used by the
system, testing the various instructions, comparing test results with an expected test
result vector quantity, and judging whether all the instructions pass a test, if yes, executing the step (4), if no, carrying out failure process; (4), carrying out
read only memory (ROM) integrity detection on operation
system files which are loaded, application programs and data, and judging whether the loaded files are integrated or not, if yes, quitting detection, if no, entering error process. Compared with the prior art, the
embedded system power on self test method has the advantages of being reliable, effective, and high in fault detect covering rate.