PCI (peripheral component interconnect) slave unit core control module applied to high-speed motion control system
A core control module, high-speed motion technology, applied in the direction of micro-control devices, etc., can solve the problems of limited embedded system design, uncustomizable functions, large space occupation, etc., to save board space, reduce external devices and wiring, improve The effect of reliability
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specific Embodiment approach 1
[0026] Specific implementation mode one: the following combination figure 1 Describe this embodiment, the PCI slave device core control module that this embodiment is applied to high-speed motion control system, it comprises core state machine, configuration unit, input and output controller, check block, RAM read and write controller and interrupt control device;
[0027] The core state machine generates different trigger signals according to the timing signals of the PCI bus, thereby controlling other modules to enter the corresponding working state, and at the same time control its own next state;
[0028] The configuration unit is used to complete the realization of configuration space registers, resource configuration, configuration operation control and address decoding;
[0029] The input and output controller is used to receive the data uploaded by the PCI bus and the secondary bus, and control the data transmission;
[0030] The check block is used to provide parity...
specific Embodiment approach 2
[0034] Specific implementation mode two: the following combination figure 2 Describe this embodiment, this embodiment will further explain Embodiment 1, the core state machine includes idle state idle, configuration operation wait state con_wait, port operation wait state io_wait, storage operation wait state mem_wait, read wait state read_wait, Configure read and write status con, port or storage read and write status rw and end status backoff;
[0035] In the idle state, the slave device does not occupy the PCI bus and waits for the read or write request initiated by the master device; when the bus command is received as a read command and the FRAME# low level information is received, it jumps to the read waiting state read_wait; when the bus is received The command is a write command, when FRAME# is low-level information, jump to the configuration operation waiting state con_wait, the port operation waiting state io_wait and the storage operation waiting state mem_wait; wh...
specific Embodiment approach 3
[0051] Embodiment 3: This embodiment further explains Embodiment 1. The configuration unit includes a configuration space register, a resource configuration module, a control configuration read and write operation module, and an address decoding module;
[0052] The configuration space register is used to realize the configuration space of the device in the configuration unit, and set the configuration register required by the PCI slave device;
[0053] Resource configuration module: after power-on, read the configuration information of the PCI device, obtain the resource request of the PCI device, and then allocate resources;
[0054] Control configuration read and write operation module: When the FRAME# signal line of PCI is pulled low and the IDSEL signal is set high, the system will read and write the configuration space of the device; at this time, the configuration unit is under the control of the core state machine Cooperate with the access operation of the master devic...
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