45results about How to "Adjust Threshold Voltage" patented technology

The invention provides an oxide semiconductor thin film and a thin film transistor. The composition of the oxide semiconductor thin film is M[2x]In[2-2x]O[3-delta], wherein M is a III B family element, x is larger than or equal to 0.001 and small than or equal to 0.3, and delta is larger than or equal to 0 and small than 3. The III B family element is one or more arbitrary elements in a group consisting of Sc, Y, Ac, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The thickness of the thin film is 5nm to 200nm. The carrier concentration of the oxide semiconductor thin film is less than 5*10<19>cm<-3>. The oxide semiconductor thin film is used as a channel layer material of the thin film transistor. The thin film transistor is provided with a gate, a channel layer, an insulated layer between the gate and the channel layer, a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected to two ends of the channel layer. The channel layer is provided with the above oxide semiconductor thin film. The oxide semiconductor thin film and the oxide semiconductor thin film have the advantages of good performance, simple preparation and wide adaptation range.

The invention discloses a buried channel transistor and a forming method thereof. The forming method comprises steps: a semiconductor substrate is provided, and a well area is formed in the semiconductor substrate; an inversion doping area is formed in the well area, the doping type in the inversion doping area is opposite to that in the well area, and the depth of the inversion doping area is smaller than that of the well area; a gate structure is formed on the surface of the semiconductor substrate above the inversion doping area, wherein the gate structure comprises a gate dielectric layer and a gate located on the gate dielectric layer, impurity ions are doped in the gate, and the doping type in the gate is the same as that in the well area; a source area and a drain area are formed inside the semiconductor substrate at two sides of the gate structure, the doping type in the source area and the drain area is opposite to the type of the impurity ions in the well area, and the depth of the source area and the drain area is smaller than that of the well area and larger than that of the inversion doping area. The transistor formed by the method of the invention can prevent generation of flicker noise and improve the device performance.

The regulator suitable for memory array with several flash memory units, each of which includes one control grid, one floating grid, one source and one drain. The regulator includes one drain power source, constant current source and control grid source. The drain power source provides one positive voltage to the drain of the flash memory unit, the constant current source provides a source current to the source of the flash memory unit, and the control grid source provides a gradually raised grid voltage to the control grid of the flash memory unit to control the source current to the flash memory unit and gradually change the critical voltage value of the flash memory unit.

The invention provides a flash memory device and a manufacturing method thereof. After the lining oxide layer is formed on the side wall of the shallow trench, P-type ion implantation is performed on the top corner of the active region of the side wall of the shallow trench to form P-type ion doping. area, to effectively improve the density of the liner oxide layer on the sidewall of the shallow trench, and to make the active area and the top boundary of the shallow trench isolation structure amorphized, with good corrosion resistance, which greatly reduces the impact of subsequent processes on the active area and the shallow trench isolation structure. The loss at the top of the top boundary of the shallow trench isolation structure reduces the depth of the pit at the top of the shallow trench isolation structure, reduces the distortion of the word line polysilicon layer formed subsequently and increases its height, and improves the narrow width effect. The off-state leakage current of the subsequently formed word line transistor is reduced and the threshold voltage thereof is increased, thereby increasing the program or program disturbance tolerance of the flash memory device. At the same time, the reliability and insulation of the subsequently formed shallow trench isolation structure are improved, and electric leakage of the shallow trench isolation structure is effectively prevented.

The invention proposes a thin film transistor and preparation method thereof, and array substrate. The thin film transistor includes a substrate, an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer and source and drain electrodes, and is characterized in that the thin film transistor also includes at least one metal oxide semiconductor layer arranged on the active layer. According to the abovementioned thin film transistor and preparation method thereof, and the array substrate, through introduction of a metal oxide semiconductor, a weak inversion heterojunction is built in the vertical direction of the transistor, characteristics of longitudinal heterojunction weak inversion are introduced into a narrow-band high-resistance region in the horizontal direction, the depletion characteristic of a junction field effect transistor is avoided, and the purposes of suppressing leakage current and adjusting threshold voltage are achieved. At the same time, the characteristic of longitudinal heterojunction inversion charge accumulation shows a large current characteristic in the horizontal direction, and a high switch ratio is realized, thereby realizing improvement of an N channel thin film transistor in performance.

A semiconductor device and a method for forming the same, wherein the method for forming the semiconductor device includes: providing a substrate, the substrate including a first semiconductor layer, an insulating layer positioned on the surface of the first semiconductor layer, and a second semiconductor layer positioned on the surface of the insulating layer, The substrate has a first region, a second region and a third region, the second region is adjacent to the first region and the third region, wherein the thickness of the insulating layer in the first region and the third region is greater than that of the insulating layer in the second region The bottom surface of the insulating layer in the first region, the second region and the third region is flush; the gate structure is formed on the surface of the second semiconductor layer in the second region; the first region and the third region on both sides of the gate structure A doped region is formed in the second semiconductor layer. The thickness of the insulating layer under the gate structure of the present invention is smaller than the thickness of the insulating layer under the doped region. Since the effective resistance of the insulating layer under the gate structure is small, the threshold voltage of the semiconductor device can be effectively improved.

Provided are a MOSFET and a manufacturing method therefor. The MOSFET comprises: a semiconductor substrate, a first buried insulating layer on the semiconductor substrate, a backgate formed within a first semiconductor layer on the first buried insulating layer, a second buried insulating layer on the first semiconductor layer, source / drain regions formed within a second semiconductor layer on the second buried insulating layer, a gate on the second semiconductor layer, and an electrical connection of the source / drain regions, the gate, and the backgate. The backgate is only arranged below one in the source / drain regions and below a channel region, and not below the other in the source / drain regions. The electrical connection comprises a public conductive channel of the backgate and of the one in the source / drain regions. The MOSFET uses asymmetric backgate to improve the suppression of a short-channel effect, and uses the public conductive channel to reduce chip footprint.

The invention provides a semiconductor structure. The structure comprises a substrate, a semiconductor substrate, back gate dielectric layers, back gates, cavities, a gate stack, side walls and source / drain regions, wherein the gate stack is arranged on the semiconductor substrate; the side walls are arranged on the side walls of the gate stack; the source / drain regions are embedded in the semiconductor substrate and are arranged on the two sides of the gate stack; the cavities are embedded in the substrate; the semiconductor substrate is suspended above the cavities; in the direction of the gate length, the middle thickness of the semiconductor substrate is greater than the thickness of the two sides; in the direction of the gate width, the semiconductor substrate is connected with the substrate; the back gate dielectric layers are arranged on the side walls of the semiconductor substrate; and the back gates are arranged on the side walls of the back gate dielectric layers. Correspondingly, the invention also provides a preparation method of the semiconductor structure. The semiconductor structure and the preparation method are beneficial to suppressing the short channel effect, adjusting the threshold voltage of the semiconductor device, improving the device performances, reducing the cost and simplifying the process.

A method for forming an MOS transistor comprises providing a substrate; forming a back gate electrode, a back gate dielectric layer, a body region, a first functional layer and a front gate dielectric layer sequentially from the bottom surface of the substrate, the first functional layer being used for increasing the rate of migration of a carrier in a channel region; etching the front gate dielectric layer and the first functional layer and forming a first groove exposing a portion of the body region; conducting ion implantation on the first groove along the body region to form a heavily doped region; filling a metal layer in the first groove and forming a plug connected with the heavily doped region; and forming a second functional layer and a front gate on the surface of a front gate dielectric layer between the heavily doped regions sequentially from the bottom to the top, the second functional layer being used for reducing the leakage current of the channel region. The method for forming the MOS transistor can adjust the threshold voltage of the formed MOS transistor, improve the compatibility and matching rate of each MOS transistor in semiconductor devices and improve the performance of formed semiconductor devices.

A buried channel transistor and a forming method thereof, the forming method comprising: providing a semiconductor substrate, forming a well region in the semiconductor substrate; forming an inversion doped region in the well region, and in the inversion doped region The type of doping is opposite to the type of doping in the well region, and the depth of the inversion doped region is smaller than the depth of the well region; a gate structure is formed on the surface of the semiconductor substrate above the inversion doped region, so The gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer, the gate electrode is doped with impurity ions, and the type of doping in the gate electrode is the same as that of the well region; A source region and a drain region are formed in the semiconductor substrate on both sides of the pole structure. The doping type in the source region and the drain region is opposite to the impurity ion type in the well region. The depth of the source region and the drain region is smaller than the depth of the well region and Greater than the depth of the inversion doped region. The transistor formed by the method of the invention prevents the generation of flicker noise and improves the performance of the device.

A forming method of a fin type field effect transistor comprises the following steps: providing a semiconductor substrate having a fin portion and a dummy grid electrode crossing a top portion and a side wall of the fin portion; forming an interlayer medium layer on the fin portion on two sides of the dummy grid electrode and the semiconductor substrate, and a top surface of the interlayer medium layer is flush with a top surface of the dummy grid electrode; etching the dummy grid electrode until the dummy grid electrode with partial thickness is left on the top of the fin portion, thereby forming a first groove; forming a first side wall on a side wall of the first groove; using the first side wall as a mask to continuously etch the dummy grid electrode through anistropic etching technology until the semiconductor substrate is exposed, thereby forming a second groove; processing the remained dummy grid electrode so as to form a second side wall; forming a metal grid electrode in the second groove comprising the second side wall. The threshold-voltage of the fin type field effect transistor formed by the method can be controlled, and the formed fin type field effect transistor has better performance.

The invention discloses a method for manufacturing a semiconductor device. The method comprises the following steps of: providing a semiconductor substrate; forming a gate layer on the semiconductor substrate; forming a blocking layer on the gate layer; etching the blocking layer and the gate layer to form a blocking pattern and a gate; washing the semiconductor substrate and the gate; forming a source electrode area and a drain electrode area in the semiconductor substrate on both sides of the gate; and removing the blocking pattern. In the method, with a blocking layer which is formed on the gate layer, impurity ions can be blocked from being filled in the semiconductor substrate below the gate layer in a process of forming the source electrode area and the drain electrode area in the semiconductor substrate on both sides of the gate, so the problem of drain current formed between the source electrode area and the drain electrode area can be solved.

The invention relates to an organic thin film transistor, which includes a mixed layer, wherein the mixed layer includes a semiconductor lower layer, a copper oxide layer and a semiconductor upper layer in order from bottom to top; the semiconductor lower layer and the semiconductor upper layer are the same or different semiconductor materials. The organic thin film transistor containing the copper oxide layer proposed by the invention can effectively adjust the threshold voltage of the organic thin film transistor. This regulation method does not need to rely on complex semiconductor doping and insulating layer surface modification technologies, and is a technology with simple processes and more suitable for commercial applications.

The invention provides a gate forming method comprising the steps of forming a single doped metal work function adjustment layer on a gate dielectric layer to enable a target work function to be between the metal work function layer and a work function of doped particles, and forming other gate layers on the metal work function adjustment layer. Through the method, the threshold voltage can be adjusted easily, the process is simple and can be implemented without multiple metal gate layers, and the manufacturing cost is reduced.