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1733 results about "Embedded processing" patented technology

Apparent network interface for and between embedded and host processors

An apparent network interface permits one processor such as a processor embedded within a larger processing system (an embedded processor) to communicate to a host processor or other processors and devices on the network to which the embedded processor is attached, using standard network communication mechanisms / protocols such as TCP / IP, NFS, FTP, HTTP, etc. The web server protocol HTTP is particularly useful because it permits the embedded computer to publish a user interface for remote monitoring and remote control using a standard web browser application. The invention provides the host computer with an apparent network interface that appears to be a standard network device, such as an Ethernet interface card. This apparent interface communicates directly with the embedded processor, which appears to be a device on this apparent network. Significant cost savings and performance enhancements are realized by implementing the communication directly over the host computer's peripheral bus rather than using standard network hardware such as Ethernet hardware.
Owner:MICROSCAN SYSTEMS

Reconfigurable test system

A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable hardware-i.e. a reconfigurable hardware module with one or more programmable elements such as Field Programmable Gate Arrays for realizing an arbitrary hardware architecture and a reconfigurable front end with programmable transceivers for interfacing with any desired physical medium-and optionally, an embedded processor. A user specifies system features with a software configuration utility which directs a component selector to select a set of software modules and hardware configuration files from a series of libraries. The modules are embedded in a host software driver or downloaded for execution on the embedded CPU. The configuration files are downloaded to the reconfigurable hardware. The entire selection process is performed in real-time and can be changed whenever the user deems necessary. Alternatively, the user may create a graphical program in a graphical programming environment and compile the program into various software modules and configuration files for host execution, embedded processor execution, or programming the reconfigurable hardware.
Owner:NATIONAL INSTRUMENTS

Novel personal electronics device

First (embedded) and second (non-embedded) processors are energized by an energy source in a hand-held device. The second processor performs functions requiring more power than those performed by the first processor. The second processor is normally asleep and is awakened by the first processor and is empowered, when awakened, to perform functions. Only the portions of the second processor required to perform these functions are activated. Protocols for functions to be performed by the second processor are provided initially to the second processor and are processed in the second processor. They are then transferred to the first processor for storage. When the second processor is activated to perform functions represented by a protocol, the protocol is transferred to the second processor and the functions are performed by the second processor.
Owner:ARM LTD

NAND Flash-based data recording method and recording controller

The invention discloses an NAND Flash-based data recording method and an NAND Flash-based data recording controller. The method comprises the following methods: a hardware bad block management method comprising the following steps of: when a sudden bad block appears, jumping to a next matched valid block without time delay to continuously record, and finally writing the data lag of a page before the bad block appears back to the jumped valid block; a hardware balance method comprising the following step of: starting the erasing-writing operation in succession to the last erasing-writing address so that the erasing-writing times of each block of the NAND Flash is approximately equal; and an input output (IO) expansion method comprising the following steps of: converting data bit width and switching control signals so that a single NAND Flash driver can control multiple chips and multiple groups of NAND Flashes. The controller comprises a ferroelectric random access memory (FRAM) controller, a top state controller, a loss equalizer, an interface switching module, a pre-matching module, an address generating module, a register set, a data verification module, a standard first in first out (FIFO) interface, a standard static random access memory (SRAM) interface, a command control interface and the NAND Flash driver. The whole controller can be mounted on a processor local bus (PLB) of an embedded processor, and data conversion between a control signal and a state signal can be performed through the command control interface and an external module.
Owner:INST OF OPTICS & ELECTRONICS - CHINESE ACAD OF SCI

Multi-protocol multi-interface wireless sensor network gateway

The invention discloses a multi-protocol multi-interface wireless sensor network gateway and relates to the technical field of a wireless sensor network. The gateway mainly consists of an embedded processor, an SDRAM (Synchronous Dynamic Random Access Memory), a Flash memory, a WiFi (Wireless Fidelity) wireless radio frequency transceiver module, a ZigBee wireless radio frequency transceiver module, a GPRS (General Packet Radio Service) module, a Bluetooth module, a GPS (Global Positioning System) data acquisition module and an Ethernet interface control module. A networked operating system Linux is used as an operating system of the multi-protocol multi-interface wireless sensor network gateway and can be compatible with a TCP / IP (Transmission Control Protocol / Internet Protocol) protocol IPv6 (Internet Protocol Version 6). The multi-protocol multi-interface wireless sensor network gateway has the advantages that conversion among various protocols is completed by treatment of a design protocol conversion program; the multi-protocol multi-interface wireless sensor network gateway can be used for setting up networks with various architectures, interconnecting the networks with various architectures and transmitting data; various network access schemes are provided for the wireless sensor network; the multi-protocol multi-interface wireless sensor network gateway has strong anti-interference capability, low power consumption and small volume; and portable equipment is provided for interconnection among the networks with various architectures and building of an integrated network.
Owner:CHINA UNIV OF MINING & TECH

High-performance low-power-consumption embedded processor based on command dual-transmission

The invention provides a high-performance low-power-consumption embedded processor based on command dual-transmission, comprising a command fetching unit, a two-way decoding unit, a transmitting unit, a command dispatch execution control unit, a command executing unit and a loading / storing unit; wherein the command fetching unit is used for pre-fetching two commands in a single clock cycle and sending the commands into an assembly line; the two-way decoding unit is used for parallelly decoding the two commands in the single clock cycle; the transmitting unit is used for parallelly transmitting the two commands in the single clock cycle; the command dispatch execution control unit is used for dynamically adjusting the command dispatch according to the computing load and controlling execution according to an out-of-order execution mechanism; the command executing unit is used for computing the results of the commands; and the loading / storing unit is used for ensuring that when the commands are absent, sequent commands can successfully occupy the assembly line and visit the data memory on the disc and the data memory outside the disc. The invention can improve the performance of the embedded processor and reduce the cost under the precondition of low power consumption.
Owner:C SKY MICROSYST CO LTD

Flexible microcontroller architecture

A microcontroller provides a flexible architecture to readily support both general embedded applications and communications applications. The microcontroller includes an embedded processor, a relatively low-speed general purpose peripheral bus controller, a relatively high-speed peripheral bus host bridge, a primary memory controller, and a secondary memory controller, each coupled to a processor bus. The general purpose peripheral bus controller is coupled to a relatively low-speed general purpose peripheral bus which is coupled to a plurality of integrated general purpose peripherals. The relatively high-speed peripheral bus host bridge is coupled to a relatively high-speed peripheral bus capable of supporting a plurality of communication-oriented peripherals. The secondary memory controller shares an address bus with the general purpose peripheral bus controller and shares a data bus with either the primary memory controller or the general purpose peripheral bus controller. The control timing of the secondary memory controller is independent of the control timing of the general purpose peripheral bus controller. Also, a processor arbiter is coupled to the embedded processor, and a relatively high-speed peripheral bus arbiter is coupled to the peripheral bus host bridge. Aside from the microcontroller, an embedded system can include a relatively low-speed general purpose peripheral bus and a relatively high-speed peripheral bus, both external to the microcontroller. The external relatively lowspeed general purpose bus can be coupled to the relatively low-speed general purpose peripheral bus controller, and the external relatively high-speed peripheral bus can be coupled to the relatively high-speed peripheral bus host bridge.
Owner:ADVANCED MICRO DEVICES INC
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